U. Glaeser

(i) Symbol rate VCO based timing recovery
Input
signal
noise
(ii) Interpolative timing recovery
Input
signal
noise
AGC
AGC
FIGURE 34.22 (i) Symbol rate VCO-based timing recovery loop. (ii) Interpolative timing recovery loop.
sampling phase τ to change. The VCO is an analog circuit under digital control. The analog part can be
a phase mixer, which is capable of adjusting the timing phase by small fractions of T where T is the
channel bit period. In such a case, the VCO acts as an amplitude to time converter and so modeled as a
simple gain. To give physical meaning to the system, the units of the signals are noted: the equalized
output after quantization by the ADC is in amplitude units of LSBs, the timing gradient ∆(k) or phase
detector output is proportional to an amplitude error and so is also in LSBs. The loop filter provides a
frequency dependent gain, so the input of the VCO is LSBs. The VCO has a gain of K V in units of T/LSB,
so the output of the VCO has units of time, T. The VCO gain can also be thought of as a clock update
gain. For the specific system we will consider later, the phase mixer can make changes in the sampling
phase in steps of 0, ±1, ±2 T/64 or more. The choice of this factor of 64 is such that the quantization of
timing phase adjustment is well below the ADC quantization noise floor.
Let us now describe the interpolative timing recovery loop of Fig. 34.22. As noted, with this scheme,
an asynchronous clock is used to sample the input to the ADC after which a FIR filter performs the
necessary equalization. The asynchronous equalized samples are now used to interpolate samples at the
correct sampling instances dictated by the partial response. This is done with the interpolation filter,
which can be thought of as a filter which delays its input by an amount τ, which is a fraction of the
channel bit period T [21]. Such an interpolation filter’s transfer function is z −τ . The samples y(k) at the
output of the interpolation filter drive the phase detector and loop filter as in the VCO-based timing
loop. The loop filter output after being processed by the phase offset calculator produces the required
sampling phase change. For good operation, the loop must be able to produce a large number of fractional
delays (such as 32 or 64) and correspondingly would require as many such filters for each of these delays.
Figure 34.22 noted that the asynchronous sampling was performed at slightly above the Nyquist rate.
The reasons for this is to accomodate a frequency offset between the written signal and the clock used
to perform the asynchronous sampling. The magnitude of this frequency offset is usually limited in
practical systems to 1% or less and so very little oversampling is required; however, oversampling ratios
© 2002 by CRC Press LLC
kT+ τ
CTF
kT
CTF
FIR
A
D
C
slightly oversampled
synchronous sampling
Interpolation
Filter
although various signals
are shown as input to the PD
only a subset of these are used
by differentPDs
A y(k) Tentative d(k) Signal Generation
Phase ∆(k)
D
Decision
Detector
C (LSB) Generation for Phase Detector
(PD) (LSB)
digital signal processing
FIR
digital signal processing
Sequence
Detector
Phase Offset
Calculation
Final decisions
τ
Tentative
Decision
Generation
Sequence
Detector
d(k)
Final decisions
Signal Generation
for Phase Detector
Loop Filter
T(z)
digital signal processing
VCO
(LSB) KV
(T/LSB)
although various signals
are shown as input to the PD
only a subset of these are used
by different PDs
Phase ∆ (k)
Detector
(PD)
analog processing
(T)
DPLL
Loop Filter
T(z)