U. Glaeser

Conclusion
An application example of an LSI chip that employs SOI devices has been described here. Against the
backdrop that the SOI CMOS process has been recognized as a key technology for increasing the
performance and reducing the power consumption of logic LSI circuits, there is a strong need by
information distribution services for LSI chips of higher performance and lower power consumption,
improvement of the quality of thin-film SOI substrates based on Si substrates, lower cost, and development
of suitability for mass production. Furthermore, progress in explaining the physical phenomena
of SOI devices is progressing, and another major factor is the establishment of control technology in
both device design and circuit design for the characteristics that bulk Si devices do not have, especially
the floating body effect. On the other hand, it is said that future LSI chips will be oriented to the systemon-a-chip
era, in which memory circuits, RF circuits, analog circuits, etc., will reside on the same chip,
rather than digital logic circuits alone. Although SOI structures are effective in reducing cross talk, as
has already been described, problems exist concerning the establishment of a precise circuit model of
the devices, which is necessary for application of SOI devices to analog circuits as well as ascertaining
the influence of the floating body effect on circuit precision. It is also necessary to continue with studies
on countermeasures for memory pass gate leakage in DRAM, SRAM, etc.
In the future, if progress in finer designs leads to the 0.1 µm era, in which the standard LSI supply
voltage will be reduced to about 1 V, we believe that the superiority of SOI CMOS over Si CMOS will
become even more remarkable.
Acknowledgments
The author thanks Y. Sato, Y. Matsuya, T. Douseki, M. Harada, Y. Ohtomo, J. Kodate, and J. Yamada for
helpful discussions and advice.
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