U. Glaeser

FIGURE 17.14 Normalized noise margin reduction due to supply bounce.
the noise margin of a standard CMOS inverter, and a more pessimistic measure of noise margin, V T.
The relative noise margin is a minimum at high voltage, such that signal integrity analysis to ensure there
is no glitching only needs to consider a single value of V DD. If a circuit passes signal integrity analysis at
maximum V DD, it is guaranteed to pass at all other values of V DD.
Supply bounce occurs through resistive (IR) and inductive (dI/dt) voltage drop on the power distribution
network both on chip and through the package pins. Figure 17.14 plots the relative normalized
IR and dI/dt voltage drops as a function of V DD. It is interesting to note that the worst-case condition
occurs at high voltage, and not at low voltage, since the decrease in current and dI/dt more than offsets
the reduced voltage swing. Given a maximum tolerable noise margin reduction, only one operating
voltage needs to be considered, which is maximum V DD, to determine the maximum allowed resistance
and inductance for the global power grid and package parasitics.
Design over Varying Voltage
One approach to designing a processor system that switches voltage dynamically is to halt processor
operation during the switching transient. The drawback to this approach is that interrupt latency increases
and potentially useful processor cycles are discarded. Since static CMOS gates are quite tolerable of a
varying V DD, there is no fundamental need to halt operation during the transient. When the gate’s output
is low, it will remain low independent of V DD, but when the output is high, it will track V DD via the PMOS
device(s). Simulation demonstrated that for a minimum-sized PMOS device in our 0.6 µm process, the
RC time constant of the PMOS drain-source resistance and the load capacitance is a maximum of 5 ns,
which occurs at low voltage. Thus, static CMOS gates track quite well for a dV DD/dt in excess of 100 V/µs,
and because all logic high nodes will track V DD very closely, the circuit delay will instantaneously adapt
to the varying supply voltage. Since the processor clock is derived from a ring oscillator also powered by
V DD, its output frequency will dynamically adapt as well, as shown in Fig. 17.15.
Yet, constraints are necessary when using a design style other than static CMOS as well as limits on
allowable dV DD/dt. The prototype processor design contains a variety of different styles, including static CMOS
logic, as well as dynamic logic, CMOS pass-gate logic, memory cells, sense-amps, bus drivers, and I/O drivers.
The maximum dV DD/dt that the circuits in this 0.6 µm process technology can tolerate is approximately
5 V/µs, which is well above the maximum dV DD/dt (0.2 V/µs) of the prototype voltage converter.
Dynamic Logic
Dynamic logic styles are often preferable over static CMOS as they are more efficient for implementing
complex logic functions. They can be used with a varying VDD, but require some additional design
considerations. One failure mode can occur while the circuit is in the evaluation state and the gate inputs
are low such that the output node is undriven at a value VDD. If VDD ramps down by more than a diode
drop by the end of the evaluation state, the drain-well diode will become forward biased. Current may
© 2002 by CRC Press LLC
Normalized ∆V/V DD
1.0
0.75
0.5
0.25
IR
dI/dt
0.0
1 2 3 4
VDD (VT )