U. Glaeser

Power consumption (W)
FIGURE 2.76 Trend in microprocessor power.
The increases in LSI speed that we have seen so far are expected to continue at least until the year 2010,
when the clock frequency should reach 10 GHz. Power consumption, on the other hand, is increasing
along with processor speed, as we see in the trend in microprocessor power consumption reported by
the International Solid-State Circuits Conference (ISSCC) (Fig. 2.76). Recently, high-performance MPUs
that operate at gigahertz speeds and consume over 100 W of power have been reported. The calculated
power density of these devices is nearly 100 W/cm 2 , and with further increases in speed, the energy
densities may approach those of a nuclear reactor [3]. This situation is recognized as a power crisis for
LSI devices, and there is a need for lower power consumption and higher speed than is being obtained
through the scaling of bulk Si devices. Furthermore, the market for portable information devices has
experienced large growth, especially cell phones. To be conveniently useful, these information devices
must be small, light, and have a sufficiently long use time under battery operation. Thus, there is a strong
demand for lowering the power consumption of microprocessors, which account for nearly half of the
power consumed by these information devices. This situation paves the way for the introduction of SOI
(silicon on insulator) CMOS (complementary metal oxide semiconductor) devices, which are suited to
low parasitic capacitance and operation on low supply voltage, as well as for the introduction of copper
lines in the LSI wiring and a low-permittivity layer between wiring layers. The history of the development
of the current SOI devices that employ a thin-film SOI substrate is shown in Table 2.3. The stream of
development, which leads to the current SOI CMOS devices that employ an SOI substrate, originated with
the forming of CMOS circuits on a SIMOX substrate for the first time in 1978 and the demonstration of
the operation of those circuits [4].
Distinctive Features of SOI CMOS Structures
A cross-section of an SOI CMOS structure is shown in Fig. 2.77. In an SOI CMOS structure, a metal
oxide semiconductor field effect transistor (MOSFET) is formed on a thin SOI layer over a buried oxide
layer, and the entire MOSFET is enclosed in a silicon oxide layer; the n-MOSFETs and p-MOSFETs are
completely separated by an insulator. Furthermore, the process technology that is required for the fabrication
of the CMOS devices is similar to the conventional bulk Si-CMOS process technology, and device
structures are also simpler than for bulk CMOS. For that reason, compared to CMOS using ordinary
bulk Si substrate, the CMOS that employ an SOI substrate have various distinctive features that result
from those structures, as shown in Fig. 2.78. Here, in particular, the features of small junction capacitance,
no substrate bias effects, and reduced cross-talk are described. These are powerful features for attaining
higher LSI performance, lower power consumption, and multifunctionality.
© 2002 by CRC Press LLC
1000
100
10
1
0.1
Data from ISSCC High performance
Low power
0. 01
1980 1985 1990
Year
1995 2000 2005