U. Glaeser

Power of these links is becoming an important issue. For many digital systems, the aggregate off-chip
bandwidth is expected to exceed terabits per second in 2010. The data rate is not expected of a single
link but over hundreds of I/Os. Each I/O cannot afford power more than a few tens of milliwatts.
These issues challenge the next generation of higher-performance link designs. The availability of faster
and more abundant transistor as CMOS technology scales will help designers face the challenges.
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