U. Glaeser

FIGURE 10.1 Typical chip interface.
The PLL generates an on-chip clock from the input clock to drive the clock distribution network and
ultimately all of the latches and registers on the chip. By sensing the clock at the input of the receiving latches
and adjusting its output phase until this latch clock aligns with the input clock, the PLL is able to subtract
out the clock distribution delay and make it appear as though the input clock directly connects to all of the
latches. The result is that the setup and hold time window is centered on the input clock edge with no process
or environmental dependencies. The amount of setup and hold time can also be controlled relative to the
clock cycle by centering the setup and hold time window relative to a different part of the clock cycle.
Although PLLs may seem to be the universal cure to all clock generation and interface problems, they
do not come without problems of their own. PLLs can introduce time-varying offsets in the phase of the
output clock from its ideal value as a result of internal and environmental factors. These time-varying
offsets in the output clock phase are commonly referred to as jitter. Jitter can have disastrous effects on
the timing of an interface by causing setup and hold time violations, which lead to data transmission errors.
Jitter was not a significant issue when PLLs were first introduced into digital IC interfaces. The
techniques employed were fairly effective in addressing the jitter issue. However, designers often reapply
those same PLL design techniques even though the nature of the problem has changed. IC technologies
have improved, leading to decreasing cycle times. The number of input/output (I/O) pins and I/O data
rates have increased leading to an increasing on-chip noise environment. An increasing aggressiveness
in I/O system design has lead to a decreasing tolerance for jitter. The result is that PLL output jitter has
increased while jitter tolerances have decreased, leading to significant jitter problems.
This chapter section focuses on the analysis and design of PLLs for interface applications in digital
ICs with particular emphasis on achieving low output jitter. It begins by considering two basic PLL
architectures in the section on “PLL Architectures.” The next two sections perform a stability analysis for
each architecture in order to gain insight into the various design tradeoffs and then present a comprehensive
design strategy to establish the various loop parameters for each architecture. More advanced
PLL architectures are briefly discussed in “Advanced PLL Architectures.” “DLL/PLL Performance Issues”
shifts gears to review the causes of output jitter in PLLs and examines circuit level techniques for reducing
its magnitude. Circuits issues related to the implementation of the various PLL loop components are
presented in the section on “DLL/PLL Circuits.” “Self-Biased Techniques” briefly discusses self-biased
techniques that can be used to eliminate the process and environmental dependencies within the PLL
designs themselves. This chapter section concludes with a presentation of PLL characterization techniques
in “Characterization Techniques.”
PLL Architectures
The basic operation of the PLLs considered in this chapter is the adjustment of the phase of the output
so that no phase error is detected between the reference and feedback inputs. PLLs can be structured in
a number of ways to accomplish this objective. Their structure can be classified based on how they react
to phase errors and how they control the phase of the output. This chapter section focuses only on PLLs
© 2002 by CRC Press LLC
CK OUT
Chip #1
D OUT
D IN
CK IN
D IN
D OUT
Chip #2
CKREF CKO CKFB PLL