U. Glaeser

delay is some fraction of the input clock period as determined by the phase detector. It is typically one,
one half, or one quarter of the input clock period.
The output delay, DO(s),
is related to the input delay, DI(s),
by
where FREF
is the reference frequency (Hz), ICH
is the charge pump current (A), C is the loop filter
capacitance (F), and KDL
is the VCDL gain (s/V). The product of the delay difference and the reference
frequency is equal to the fraction of the reference period in which the charge pump is activated. The average
charge pump output current is equal to this fraction times the peak charge pump current. The output delay
is then equal to the product of the average charge pump current, the loop filter transfer function, and the
delay line gain.
The closed-loop response is then given by
where
© 2002 by CRC Press LLC
DO(
s)
�DI(
s)
= 1/(
1 + s/ ωN)
ω N,
defined as the loop bandwidth (rad/s), is given by
ωN
= ICH
⋅ KDL
⋅ FREF�C
This response is of first order with a pole at ω N.
Thus, the DLL acts as a single-pole low-pass filter to
changes in the input reference period with cutoff frequency ωN.
The delay between the reference and
feedback signal will be a filtered version of a set fraction of the reference period. It is unconditionally
stable as long as the continuous time approximation holds or, equivalently, as long as ω N is a decade
below ωREF.
As ω N increases above ωREF/10,
the delay in sampling the phase error will become more
significant and will begin to undermine the stability of the loop.
DLL Design Strategy
With an understanding of the DLL frequency response, we can consider how to structure the loop
parameters to obtain desirable loop dynamics. Using the bandwidth results from the DLL frequency
response and, limiting it to a decade below the reference frequency, we can determine the constraints on
the charge pump current, VCDL gain, and loop filter capacitance as
ω N�
FREF
= Ich
⋅ KDL�
C ≤ π �5
The VCDL also must be structured so that it spans adequate delay range to guarantee lock for all
operating, environmental, and process conditions. The delay range needed is constrained by the lock
target delay of the phase detector, TLOCK,
and the range of possible values for the clock distribution delay,
, and the reference period, T , with the following equations:
T
DIST
DO () s = ( DI() s – DO() s ) ⋅ FREF ⋅ ICH � ( s⋅C) ⋅ KDL CYCLE
VCDLMIN = TLOCK – TDIST__MAX VCDLMAX =
TLOCK – TDIST__MIN ( ) modulo T CYCLE_MIN
( ) modulo T CYCLE_MAX
where TLOCK
is 1 cycle for in-phase locks and 1/4 cycles for quadrature locks.
Also, special measures may be required to guarantee that the DLL reaches lock after being reset. These
measures depend on the specific structure of the DLL. Typically, the VCDL delay is set to its minimum
delay and the state of the phase detector is reset. However, for some DLLs, more complicated approaches
may be required.
Alternative DLL Structures
The complexity of designing a DLL is not so much in the control dynamics as it is in the underlying structure.
Although the DLLs discussed in this chapter are analog-based, using VCDLs with analog control, many other
approaches are possible that utilize different amounts of analog and digital control. These approaches can