U. Glaeser

FIGURE 29.3
FIGURE 29.4
29.4 Low-Power Design in Application-Specific DSPs
Low-power design approaches in application-specific DSPs exhibit more breadth and innovation due to
the fact that such designs target a well defined problem as opposed to a wide range of possible applications.
Classification of such design techniques can by no means be complete due to continuous novelties in
circuit and system designs improving DSP system power performance. In this section, technology and
low-level circuit issues are not addressed because they were briefly addressed earlier and are also relevant
to general-purpose DSP systems. Instead, the focus is on unique application-specific power reduction
techniques that have been reported in the literature during the last few years.
Variable Supply Voltage Schemes
Embedded adaptive supply scaling has been the focus of multiple investigators due to the potential for
substantial power savings in both fixed and variable throughput systems.
Nielsen et al. [14] have demonstrated a self-timed adaptive supply voltage system that takes advantage
of variable computational loads (Fig. 29.4(a)). The self-timed system operates in a synchronous environment
and is enclosed between rate-matching FIFO buffers. The state detecting circuit monitors the
state of the input FIFO, which is an indicator of remaining workload. If the buffer is relatively full, the
supply voltage is increased and the circuit operates faster to keep up with the load. If the FIFO is relatively
empty the supply voltage is reduced because the circuit operates too fast. In this way, the supply voltage
is optimally adjusted to the actual workloads maintaining the throughput requirements at all times. Wei
and Horowitz [15] have investigated techniques for low-power switching supplies for similar applications.
Gutnik [16] has demonstrated a synchronous implementation of a variable supply voltage scheme that
uses FIFO state to generate both a supply voltage and a corresponding variable clock using a closed-loop
ring oscillator (Fig. 29.4(b)). As the FIFO fills up the clock speed increases to sustain the higher workload
and as the FIFO empties the clock slows and the supply voltage decreases for quadratic power reduction.
© 2002 by CRC Press LLC
Clock-gating.
Master CLK
Adaptive supply voltage schemes.
D Q Combinational
Logic
D Q
EN0
I0 I1
EN1
I2 I3
State
Detect
DC/DC
Converter
V DD
Asynchronous
FIFO FIFO
DSP
(a) Asynchronous Adaptive Supply Scheme
Rate
Control
Workload
Filter
FIFO
Voltage
Reg
V DD
Ring
Osc
Synchronous
DSP
CLK
(b) Synchronous Adaptive Supply Scheme