U. Glaeser

Chouki Aktouf
Institute Universitaire
de Technologie
46.1 Introduction
© 2002 by CRC Press LLC
46
Scan Testing
46.1 Introduction
46.2 Scan Testing
Boundary Scan • Partial Scan • Scan and Built-in Test
Solutions • Tools and Languages for Scan Automation
46.3 Future of Scan: A Brief Forecast
Scan for Analog and Mixed Designs • RTL
and Behavioral Scan
Given a design under test (DUT), a test s olution is qualified as efficient if it allows the generation of
test patterns, which enable the detection of most of possible physical faults that may occur in the design.
Researchers talk about 99% of fault coverage and more. To reach such a test efficiency, the cost to pay is
related to time which is necessary for test pattern generation and application, the area overhead for the
added logic, the added number of pins, etc. These parameters are concerned through scan testing techniques,
which are presented in the next section.
Some studies have shown that the testing phase can constitute a serious problem in the overall
production time. For typical circuits, testing can take from the one-third to the half of the total time to
market (TTM) [1]. In [2], it has been shown that a design-for-testability (DFT) technique such as full
scan can reduce by more than a half the total engineering costs. Indeed, scan helps in detecting a fault
quickly and in an efficient manner.
As shown in Fig. 46.1 the well-known “rule of ten” is true when scan is considered. Indeed, sooner a
fault is detected the lower is the subsequent cost. This is explained by the fact that DFT helps in the
generation of efficient test patterns. In other words, given in a short period of time, if a fault appears in
a DFT-based design, a high probability exists to detect the fault. Furthermore, a DFT technique such as
scan helps in the testing through the whole life cycle of the design including debug, production testing,
and maintenance.
46.2 Scan Testing
Today, given strong time to market constraints on new products, only DFT is capable of ensuring the
design of complex system-on-chips with a high testing quality. Scan is widely used in industry. It took
almost 20 years to reach such a maturity, even if some designers still think that scan penalizes a design
due to the required cost and performance degradation.
Scan testing is applied to sequential testing, i.e., testing of sequential designs. It relates to the ability
of shifting data in and out of all sequential states. Regardless to the used scan approach, all flip-flops are
interconnected into one or more shift registers that ensures the shifting in and the shifting out functions.
The built shift register is fully controlled/observed from primary inputs/outputs as shown in Fig. 46.2 [3].