U. Glaeser

The opcode statement assigns instruction fields with values. The operand statement specifies how an
instruction’s operand is encoded in an instruction field. The iclass statement describes the assembly
format for an instruction and lists the input and output operands of the instruction. A large set of predefined
instruction fields and operands (used to describe the base Xtensa ISA) can be used directly in
the TIE description. The following example describes two instructions: A4 and S4. These instructions
take two 32-bit operands from the core register file, perform four 8-bit additions and subtractions and
store the result back to the core register file:
© 2002 by CRC Press LLC
opcode A4 op2 = 0 CUST0
opcode S4 op2 = 1 CUST0
iclass RR {A4, S4} {out arr, in ars, in art}
The first two lines define the opcodes for A4 and S4 as sub-opcodes of a previously defined opcode
CUST0 with the addition of field op2 equal to 0 and 1, respectively. The third line makes use of the predefined
register operands arr, ars, and art, and defines two new assembly instructions,
A4 arr, ars, art
S4 arr, ars, art
Customized Datapath
The computational part of an instruction is specified in a TIE reference block. The syntax of a reference
block is very similar to the Verilog hardware description language. The variables used in the reference
block are predefined (if they appear in the iclass statement), or locally declared variables. The
reference block for the A4 and S4 instructions defined in the previous section are shown below,
reference A4 {
}
assign arr = {
ars[31:24] + art[31:24],
ars[32:16] + art[23:16],
ars[15:8] + art[15:8],
ars[7:0] + art[7:0]};
reference S4 {
}
assign arr = {
ars[31:24] - art[31:24],
ars[32:16] - art[23:16],
ars[15:8] - art[15:8],
ars[7:0] - art[7:0]};
The reference description for the two instructions is simple and direct, yet may not result in the best
hardware implementation. For example, the logic for addition and subtraction could be shared between
the two instructions. TIE allows the designer to describe this high-level hardware sharing between
multiple instructions using the semantic block. The semantic block is similar to a reference