U. Glaeser

FIGURE 6.16 The placement of the branch prediction components in the pipeline.
will be the appropriate target address. As branches change their taken/not-taken behavior, this next-line
address is updated accordingly. The next-line predictor is, therefore, a combination of the functionality
of a BTB and a bimodal predictor (see the section on “Bimodal Prediction”). If a more sophisticated
direction predictor is present, it overrides the next-line predictor. One motivation for using such an
organization is to permit a larger, slower, but more accurate direction predictor that may not be able to
be accessed in a single cycle. The Alpha 21264 takes such an approach [25], using as its slower but more
accurate direction predictor the hybrid predictor described in the section on “Hybrid Prediction.”
Pipeline Issues
In the most efficient organization, both the BTAC and the branch direction predictor are consulted during
the fetch stage as shown in Fig. 6.16. In this way, the PC can be updated immediately and the processor
can fetch from the appropriate location (taken or not-taken) in the next cycle. This avoids introducing
pipeline bubbles unless there is a BTAC miss or a branch misprediction.
Unfortunately, some problems occur with probing the branch-prediction hardware in the fetch stage.
One concern is the branch-predictor and BTAC lookup times. These tables must be fast enough, and
hence small enough, to permit the lookup to complete and the PC to be updated within a single cycle.
Otherwise the fetch stage falls behind. Current processors use predictors as big as 32 kbits, but Jiménez
et al. [26] argue that the feasible predictor size for single-cycle access will shrink in the coming years.
The reason for this is that even though the feature size on a processor die continues to shrink with
Moore’s law [27], electrical RC delays are not shrinking accordingly, and hence wire delays are not
shrinking as fast as logic delays. As feature size shrinks, large structures therefore seem to be getting
relatively slower.
Another problem is that in a typical organization, the fetch stage cannot determine whether the
instructions being fetched from the instruction cache contain any branches; that information must wait
until the instructions are decoded. Several solutions are available. The first technique is for the instructions
to be “pre-decoded” before they are installed into the instruction cache to indicate which instructions
are branches. The predictor structures can then be indexed using the actual addresses of the
branches. Note that this means either that the predictor must be multi-ported to cope with fetch blocks
that contain more than one branch, or the predictor can only predict one branch at a time. This is not
necessarily a major restriction, since if the predicted result is not-taken, the remaining instructions in
© 2002 by CRC Press LLC
mux
mux
+
PC
4
I-cache
bpred
BTAC
fetched instructions
T/NT
BTB hit?
predicted taken target
computed taken target, from decode
to decode