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10.2 Latches and Flip-Flops
Fabian Klass
Introduction
This chapter section deals with latches and flip-flops that interface to complementary static logic and are
built in CMOS technology. Two fundamental types of designs are discussed: (1) design based on transparent
latches and (2) designs based on edge-triggered flip-flops. Because conceptually flip-flops are built
from transparent latches, the analysis of timing requirements is focused primarily on the former. Flipflop-based
designs are then analyzed as a special case of a latch-based design. Another type of latch, known
as a pulsed latch, is treated in a special section also. This is because while similar in nature to a transparent
latch, its usage in practice is similar to a flip-flop, which makes it a unique and distinctive type.
The chapter section is organized as follows. The first half deals with the timing requirements of latchand
flip-flop-based designs. It is generic and the concepts discussed therein are applicable to other technologies
as well. The second half of the chapter presents specific circuit topologies and is exclusively focused
on CMOS technology. Various latches and flip-flops are described and their performance is analyzed. A
subsection on scan design is also provided. A summary and a historical perspective is finally presented.
Historical Trends
In discussing latch and flip-flop based designs, it is important to review the fundamental concept behind
them, which is pipelining. Pipelining is a technique that achieves parallelism by segmenting long sequential
logical operations into smaller ones. At any given time, each stage in the pipeline operates concurrently
on a different data set. If the number of stages in the pipeline is N, then N operations are executed in
parallel. This parallelism is reflected in the clock frequency of the system. If the clock frequency of the
unsegmented pipeline is Freq, a segmented pipeline with N stages can operate ideally at N × Freq. It is
important to understand that the increase in clock rate does not necessarily translate linearly into increased
performance. Architecturally, the existence of data dependencies, variable memory latencies, interruptions,
and the type of instructions being executed, among other factors, contribute to reducing the
effective number of operations executed per clock cycle, or the effective parallelism [1]; however, as a
historical trends show, pipelines are becoming deeper, or correspondingly, the stages are becoming
shorter. For instance, the design reported in [2] has a pipeline 15-stage deep. From a physical perspective,
the theoretical speedup of segmentation is not attainable either. This is because adjacent pipeline stages
need to be isolated, so independent operations, which execute concurrently, do not intermix. Typically,
synchronous systems use latches or flip-flops to accomplish this. Unfortunately, these elements are not
ideal and add overhead to each pipeline stage. This pipeline overhead depends on the specific latching
style and the clocking scheme adopted. For instance, if the pipeline overhead in an N-stage design is 20%
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