U. Glaeser

FIGURE 1.11 Top view of 40 nm gate length MOSFETs [4].
FIGURE 1.12 Cross-sectional TEM image of 1.5 nm gate oxide [5].
decreased to 0.3–0.25 V and further reduction causes significant increase in subthreshold leakage current.
Further reduction of the threshold voltage and thus the further reduction of the supply voltage are difficult.
In 1990s, fortunately, those difficulties were shown to be solved somehow by invention of new techniques,
further modification of the scaling, and some new findings for short gate length MOSFET operation. In
the following, examples of the solutions for the front end of line are described. In 1993, first successful
operation of sub-50 nm n-MOSFETs was reported [4], as shown in Fig. 1.11. In the fabrication of the
MOSFETs, 40 nm length gate electrodes were realized by introducing resist-thinning technique using oxygen
plasma. In the scaling, substrate (or channel doping) concentration was not increased any more, and the
gate oxide thickness was not decreased (because it was not believed that MOSFETs with direct-tunnelling
gate leakage operates normally), but instead, decreasing the junction depth more aggressively (in this case)
than ordinary scaling was found to be somehow effective to suppress the short-channel effect and thus to
obtain good operation of sub-50 nm region. Thus, 10-nm depth S/D junction was realized by introduction
of solid-phase diffusion by RTA from PSG gate sidewall. In 1994, it was found that MOSFETs with gate
SiO 2 less than 3 nm thick—for example 1.5 nm as shown in Fig. 1.12 [5]—operate quite normally when
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