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U. Glaeser

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FIGURE 29.7 DCT Chip [my DCT] average power vs. compressed image quality.<br />

FIGURE 29.8 Compressed image quality and power.<br />

Amirtharajah et al. [34,36] use a similar DA-based approximate processing technique in a programmable<br />

ultra-low-power DSP targeted to physiological monitoring. Reduced RAC iterations reduce the<br />

signal to noise ratio of the input signal (effectively increasing the quantization noise) and result in less<br />

reliable heart beat detection. Yet, the reduced performance results in linear power savings, which may be<br />

desirable in certain situations.<br />

29.5 Conclusion<br />

This chapter has presented a collection of power reduction techniques that applied in DSP applications<br />

during the last few years. Although presented in a categorized form to provide structure in the exposition,<br />

the author does not believe that true low-power design involves a laundry list of power reduction<br />

techniques and blind application to the problem in question. Instead, low-power design involves a vertical<br />

design process and a global optimization across algorithmic, architectural, circuit, and physical design<br />

boundaries. A designer must have a deep understanding of the DSP application under power optimization.<br />

The best algorithm must be selected, which minimizes a weighted average of the number of<br />

arithmetic operations, memory accesses, on-chip communication, and silicon area. The right boundary<br />

must be achieved between programmability and predefined functionality. Architectural, circuit, and<br />

physical design techniques must then be applied that fully support the algorithmic selection but at the<br />

same time should be allowed to influence such selection in order to achieve optimum results.<br />

The author concludes by enumerating a few case studies, which demonstrate concurrent optimization<br />

across all design phases and as a result have achieved impressive results in a few key DSP application areas.<br />

Chandrakasan et al. [35] have demonstrated a low-power chipset for a portable multimedia terminal.<br />

This work was power optimized from a system perspective and performed a number of functions such as<br />

protocol conversion, synchronization, and video decompression, among others, while consuming under<br />

5 mW of power. Amirtharajah [36] has demonstrated an ultra-low-power programmable DSP for physiological<br />

monitoring (heartbeat detection and classification). His techniques involved algorithmic design,<br />

© 2002 by CRC Press LLC<br />

Power (mW)<br />

5.5<br />

5<br />

4.5<br />

4<br />

3.5<br />

3<br />

20 25 30 35<br />

PSNR (dB)<br />

40 45 50<br />

23.99 dB 3.07 mW 32.46 dB 4.30 mW 44.84 dB 5.11 mW

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