U. Glaeser

FIGURE 2.66 Circuit diagram of 3-input OR/NOR function [22].
3-input AND/NAND gates were implemented as cascade of 2-input gates with balanced loads, the loading
would remain balanced.
The example in Fig. 2.65 also illustrates the reduction in transistor count by overlapping cubes C 1 and
C 3. The consequence of the overlapping is that both of the corresponding branches are simultaneously
pulling down for those input vectors under which the cubes overlap. Direct realization of 3-input OR/NOR
circuit, Fig. 2.66, is straightforward if complementarity and duality are applied to circuit in Fig. 2.65. A
three-input XOR/XNOR circuit in CPL is typically composed of 2-input XOR/XNOR modules [3].
Synthesis of CMOS PTL Networks (DPL and DVL)
Synthesis of DPL
DPL has twice as many transistors as CPL for the same logic function. Consequently, the synthesis of
double pass-transistor logic is based on covering every input vector in the Karnaugh map twice. The idea
is to assure all logic “0”s in the map are passed to the output through at least one NMOS branch and all
logic “1”s through at least one PMOS branch.
The rules to synthesize random logic function in DPL from its Karnaugh map are:
1. Two NMOS branches cannot be overlapped on logic “1”s. Similarly, two PMOS branches cannot
be overlapped on logic “0”s.
2. Pass signals are expressed in terms of input signals or supply. Every input vector has to be covered
with exactly two branches.
Complementarity principle: The complementary logic function in DPL is generated after the following
modifications of the true function: (1) swap PMOS and NMOS transistors, and (2) invert all pass and
gate signals. Unlike purely NMOS pass-transistor networks, in CMOS networks both pass and gate signals
need to be inverted because the PMOS and NMOS transistors are swapped in step (1).
Duality principle: The dual logic function in DPL is generated when PMOS and NMOS transistors are
swapped, and V dd and GND are swapped.
The procedure to synthesize DPL circuits is illustrated on the example of 2-input AND circuit shown
in Fig. 2.67. Cube C1, Fig. 2.67(a), is mapped to an NMOS transistor, with the source connected to
ground and the gate connected to B.
Cube C2 is mapped to a PMOS transistor, which passes A, when
gate signal B
is “low.” The NMOS transistor of C3 pulls down to ground, when A is “low,” and the PMOS
transistor of C4 passes B, when A is “high.” Complementary circuit (NAND), Fig. 2.67(b), is generated
from AND, by applying the complementarity principle. Following the duality principle, OR circuit is
formed from AND circuit, Fig. 2.68.
Different 2-input XOR/XNOR circuit arrangements are possible, depending on mapping strategy.
Fig. 2.69 shows a realization with balanced load on both true and complementary input signals. Threeinput
functions in DPL are implemented as cascaded combinations of 2-input DPL modules.
© 2002 by CRC Press LLC
A
A
B
B
A C B A C B
OR
NOR