U. Glaeser

[KSR91] KSR-1 Overview, Internal Report, Kendall Square Research Co.170 Tracer Lane, Waltham, MA
02154, 1991.
[Lam88] M. Lam Software Pipelining, “An Effective Scheduling Technique for VLIW Machines,” ACM
Sigplan 1088 Conf. or Programming Language Design and Implementation, 1988.
[Leiserson92] C. E. Leiserson, “The Network Architecture of the Connection Machine, CM-5,” Proc. ACM
Symp. Computer Architecture, 1992.
[Lo97] J. Lo, S, Eggers, et al., “Tuning Compiler Optimization for Simultaneous Multithreading,” Int.
Symp. on Microarchitecture, 1997.
[MasPar91] MasPar, “The MasPar Family of Data Parallel Computer,” Technical summary, MasPar Computer
Corporation, Sunnyvale, CA, 1991.
[May88] D. Pountain and D. May, Occam Programming, INMOS, Oxford England, 1988.
[Miller90] D. R. Miller and D. J. Quammen. “Exploiting Large Register Sets,” Int. J. Microprocessors and
Microsystems, pp. 333–340, August 1990.
[Park97] S. Park, S. Shim, and S. Moon, Evaluation of Scheduling Techniques on a SPARC-Based VLIW
Testbed, Micro-30, 1997.
[Polychronopulos89] C. D. Polychronopulos, et al., “Paradrase 2: An Environment for Parallel zing, Partitioning,
Synchronizing Programs on Multiprocessors,” Proc. Int. Conf. on Parallel Processing, 1989.
[Quammen96] D. Quammen, J. Stanley, and P. Wang, “The Packed Exponential Connection Network,”
Pre. Int. Symp. Parallel Arch. Algorithms and Networks, 1996.
[Rau93] B. Rau and J. Fisher, “Instruction-Level Parallel Processing: History, Overview, and Perspective,”
J. Supercomputing: Special Issue on Instruction-Level Parallelism, 1993.
[Saulsbury95] A. Saulsbury, T. Wilkinson, et al., “An Argument for a Simple COMA,” Symp. Int. on High
Perf. Computer Architecture, 1995.
[Siegel89] H. J. Siegel, “A model of SIMD Machines and a Comparison of Various Interconection
Networks,” IEEE Trans. Computer, 28(12) 1989.
[Smith90] J. E. Smith, “Future General-Purposes Supercomputer Architecture,” Proc. ACM Supercomputing
Conf., 1990.
[Tullsen95] D. Tullsen, et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” Proc.
23rd Int. Symp. on Computer Architecture, 1995.
[Wolfe91] M. E. Wolfe and M. Lam, “A Loop Transformation Theory and an Algorithm to Maximize
Parallelism,” IEEE Trans. Parallel Distri Systems, 3(10), 1991.
[Yuan97] X. Yuan, R. Melhem, and R. Gupta, “Distributed Path Reservation Algorithms for Multiplexing
All-Optical Interconnection Networks,” Proc. Symp. High-Performance Comp. Architecture,
1997.
5.6 Virtual Memory Systems and TLB Structures
Bruce Jacob
Virtual Memory, a Third of a Century Later
Virtual memory was designed in the late 1960s to provide automated storage allocation. It is a technique
for managing the resource of physical memory that provides to the application an illusion of a very large
amount of memory—typically, much larger than is actually available. In a virtual memory system, only
the most often used portions of a process’s address space actually occupy physical memory; the rest of
the address space is stored on disk until needed. When the mechanism was invented, computer memories
were physically large (one kilobyte of memory occupied a space the size of a refrigerator), they had access
times comparable to the processor’s speed (both were extremely slow), and they came with astronomical
price tags. Due to space and monetary constraints, installed computer systems typically had very little
memory—usually less than the size of today’s on-chip caches, and far less than the users of the systems
would have liked. The virtual memory mechanism was designed to solve this problem, by using a system’s
disk space as if it were memory and placing into main memory only the data used most often.
© 2002 by CRC Press LLC