U. Glaeser

and validated for design specs. As design flows into lower level of abstraction it becomes more complex
and design changes become more difficult. So, it is advisable to start design trade-offs at the early stage
of the design—HLM or RTL. Also, the higher level of abstraction allows greater impact on the design
with less effort. So, power estimation tools are needed at all design levels. At the early stage they are needed
to make smart decisions about power-performance trade-offs, and at lower levels to validate design changes
and to quantify impact of design changes.
Issues in Power Estimation
How do you know how much power your design will consume before plugging the chip into your board
and measuring it? To perform these calculations, knowing the circuit’s clock frequencies and the multiplicative
constants (activity factors) provided by the vendor can help to some extent. But the more difficult
parameter to be determined is the average number of flip-flops and routing nodes that transition during
each clock edge. Determining this value is especially tough for hardware description language-based
designs, as one may have little or no insight into the logic implementation of the chosen device. Some
vendors suggest the use of a 12.5% usage estimate (refer to the section on “Switching Power,” where this
amounts to N = 0.125) corresponding to the average toggle percentage of a 16-bit counter. Others believe
that a 25% estimate for an 8-bit counter is more typical. Some circuits, such as arithmetic units, have
even higher toggle percentages. The choice can radically impact the accuracy of the estimate.
In general, the most effective design decisions can be derived from choosing and optimizing algorithms
at the highest level of the design hierarchy. This dictates the need for an effective high-level power
estimation tool. In the absence of a high-level power analysis tool, the designer has to first synthesize and
validate the functionality of a lower-level netlist, and then run a logic or transistor-level power analysis
tool to estimate power consumption. The large iteration times of lower-level power analysis tools, and
the long time required to obtain and validate a gate-level or transistor-level netlist, makes this methodology
inefficient to estimate power. At the same time, there is a penalty associated with high-level power
estimation tools. The absolute accuracy of high-level power estimation tool tends to be lower than the
accuracy provided by using low-level estimation tools. These are some of the issues in power estimation
that need to be considered for a good design. In the following section, several power estimation tools
operating at different levels of design abstraction are discussed.
Power Estimation Techniques
Power estimation techniques can be broadly classified into statistical, probabilistic, and macromodeling
techniques. In statistical techniques, the circuit is simulated using a timing or logic simulator, while
monitoring the power being consumed. This procedure is repeated for various sets of input vectors until
a desired level of accuracy is achieved. Eventually power converges to the average value. One example of
accurate statistical analysis method is the activity-based control model. This model expresses the complexity
of control units and input activities making it easy to analyze the power consumption of regular
implementations, such as ROM and PLA-based structures.
In probabilistic techniques, the signals are represented with probabilities that substitute for the time
consuming simulations; however, there is a loss in accuracy. The signal probability is defined as the
probability of having a logic value of “1” on a signal and the transition probability represents the probability
of the proportion of transitions on the signal. These probabilities lead to a simple computation of
switching activity, the parameter that needs to be determined for power computation. The simplest way
to propagate probabilities is to work at the gate-level description of the circuit. When the circuit is built
from Boolean components that are not part of a predefined gate library, the signal probability can be
computed by using a binary decision diagram (BDD) to represent the Boolean functions.
Another popular approach, mostly used for high level power estimation is the macromodeling technique.
In this method, a macromodel is constructed by obtaining and characterizing a lower-level
implementation. Based on the power consumption characteristics of the macroblock for various training
sequences, a macromodel or function is then constructed that describes the power consumption of the
© 2002 by CRC Press LLC