U. Glaeser

FIGURE 42.60 Basic pipeline architecture for a RISC and a DSP processor.
Program instruction order
Program instruction order
Program instruction order
Fetch
Fetch
FIGURE 42.61 Memory-intensive number crunching on a RISC and a DSP.
accumulator is set. In the simple examples of Fig. 42.62, there needs to be two, respectively three instruction
cycles between the setting of the accumulator flag and the usage of it in the decode stage, by the RISC
and DSP processor, respectively. Therefore, the RISC has an advantage for control dominated applications.
In practice these pipeline hazards are either hidden to the programmer by hardware solutions (e.g.,
forwarding or stalls) or they are visible to the programmer, who can optimize his code around it. A typical
example are the branch and the “delayed branch” instruction in DSP processor. Because an instruction is
fetched in the cycle before it is decoded, a regular branch instruction will incur an unnecessary fetch of the
next instruction in memory following the branch. To optimize the code in DSP processors, the delayed
branch instruction is introduced. In this case, the instruction that follows the branch instruction in memory
will be executed before the actual branch takes place. Hence, a delayed branch instruction takes effectively
one cycle to execute while a regular branch will take two cycles to execute.
© 2002 by CRC Press LLC
Fetch
Fetch
Decode
(a) RISC pipeline
Decode
(b) DSP pipeline
Decode Execute
Fetch
Decode Execute
Fetch
Memory
Access
(a) RISC pipeline
Execute
Memory
Access
Memory
Access
Write
Back
Memory access / branch
Execution/ address generation
Execute
Time in clock cycles
Write
Back
Execution
Memory access/address post modification
Write
Back
Memory
Access
Decode Execute
Time in clock cycles
Write
Back
Memory
Access
Write
Back
Time in clock cycles
Memory
Write
Decode Execute
a0 = a0 + *p0;
Access
Back
(b) DSP pipeline
r0 = *p0; // load data
a0 = a0 + r 0 // operate