U. Glaeser

whitening the noise prior to the Viterbi detector. The whitened total distortion component of the PR
equalized output y n is
where the N-coefficient MMSE predictor transfer polynomial is P(D) = p1D 1 + p2D 2 + … + pND N . Note
that an estimate of the current noise sample wˆ n is formed based on estimates of previous N noise samples.
Assuming the PR4 equalization of sequence y, the metric of the Viterbi detector can be modified in order
to compensate for distortion component. In this case, the equalizer output is yn = xn − xn−2 + wn and the
NPML distance is
where xˆ n−i( Sj) , xˆ n−i−2 ( Sj) represent past decisions taken from the Vitrebi survivor path memory associated
with state Sj. The last expression gives the flavor of this technique, but it is not suitable for
implementation so that the interested reader can find details in [20] how to modify this equation for
RAM look-up realization. Furthermore, in the same paper, a description of the general procedure to
compute the predictor coefficients based on the autocorrelation of the total distortion wn at the output
of a finite-length PR equalizer is given.
Postprocessor
As explained earlier, Viterbi detector improves the performance of a read channel by tracing the correct
path through the channel trellis [8]. Further performance improvement can be achieved by using soft
output Viterbi algorithm (SOVA) [14]. Along with the bit decisions, SOVA produces the likelihood of
these decisions, that combined create soft information. In principle, soft information can be passed to
hard drive controller and used in RS decoder that resides there, but at the present time soft decoding of
RS codes is still too complex to be implemented at 1 Gb/s speeds. Alternatively, much shorter inner code
is used. Because of the nonlinear operations on bits performed by the modulation decoder logic, the
inner code is used in inverse concatenation with modulation encoder in order to simplify calculation of
bit likelihood. Due to the channel memory and noise coloration, Viterbi detector produces some error
patterns more often than others [5], and the inner code is designed to correct these so-called dominant
error sequences or error events. The major obstacle for using soft information is the speed limitations and
hardware complexity required to implement SOVA. Viterbi detector is already a bottleneck and the most
complex block in a read channel chip, occupying most of the chip area, and the architectural challenges
in implementing even more complex SOVA would be prohibitive. Therefore, a postprocessor architecture
is used [18]. The postprocessor is a block that resides after Viterbi detector and comprises the block for
calculating error event likelihood and an inner-soft error event correcting decoder.
The postprocessor is designed by using the knowledge on the set of dominant error sequences E =
{ei} 1≤i and their occurrence probabilities P = (pi) 1≤i
. The index i is referred to as an error type, while
the position of the error event end within a codeword is referred as an error position. The relative frequencies
of error events will strongly depend on recording density [36]. The detection is based on the fact that
we can calculate the likelihoods of each of dominant error sequences at each point in time. The parity
bits detect the errors, and provide localization in error type and time. The likelihoods are then used to
choose the most likely error events for corrections.
© 2002 by CRC Press LLC
N
∑
N
wn – wˆ n = wn – ∑w
n−ip i
i=1
⎛ ⎞
⎜yn– wn−ip i⎟
– ( xn( Sk) – xn−2 ( Sj) )
⎝ i=1 ⎠
=
N
∑
⎛ ⎞
⎜yn– ( yn−i – xˆn−i ( Sj) – xˆ n−i−2 ( Sj) )pi⎟ – ( xn( Sk) – xn−2 ( Sj) )
⎝ i=1
⎠
2
2