U. Glaeser

FIGURE 11.2
output impedance current sources improves the gain, but reduces the output voltage swing and increases
the comparator delay. Our characterization of test circuits with threshold currents between 5 and 100 µ A
fabricated in 2-µ
m p-well CMOS shows best input-current/output-voltage propagation delays of approximately
2 ns. The best reported delay performance of a similar circuit that defines the output as the
difference of the two drain currents, not the drain voltage, has been reported to be 500 ps in a ring
oscillator [21] realized in 2-µ
m p-well CMOS.
To improve the delay performance of the comparator, we may provide a DC bias current to the input
transistor to keep it biased in a conducting state. The change in input current then exceeds the biasshifted
reference threshold current. Delay improvements of more than 50% have been observed.
MVL circuits often realize threshold logic functions with several thresholds. This requires the comparison
of the input current to several different threshold currents. It is possible to simply replicate the
input current as many times as needed and compare these multiple copies of the input current to the
set of increasingly larger threshold currents. Increased threshold current reduces the comparator gain.
To keep gain higher, it is also possible to scale the input current to several different values (some of which
may be smaller than the input) and then compare these scaled input currents to a set of smaller reference
threshold currents. Design strategies that scale the input current and the threshold currents may be
developed to optimize area, speed, and total current. For ease of explanation in this presentation, our
discussions present the simplest approach: merely duplicating the input current and creating a set of
linearly spaced, increasingly larger reference threshold currents.
© 2002 by CRC Press LLC
CMOS current comparator.