U. Glaeser

FIGURE 14.12 Data enabling.
In addition, this also helps the di/dt issues on the chip as sub-regions/blocks will be turned off selectively.
Although this technique offers great power saving advantages, it also carries a few design challenges.
Some of the concerns in clock gating are that the disabled block may not power up in time and also that
modified clocks may generate glitches. As a result the enable signals will have a very strict timing requirement.
In addition, at high frequencies, clock skew becomes a significant portion of cycle time and the gated
clocks will add to the clock network skews, thus becoming undesirable. Therefore, the granularity at
which clock gating can be applied becomes a tradeoff against overall clock network design time and
complexity. Some other side effects of clock gating that a designer needs to consider are the area penalty
due to generation of the enable signal, clock gating elements, and also the routing overhead to distribute
enable signals.
An alternate method for power saving is through data enabling. Data enabling implementation is
shown in Fig. 14.12. The enable signal generates a data enable signal that indicates whether the current
data is valid or not. This prevents input data updates for invalid data or an idle condition. Thus it avoids
unnecessary transitions within the design. One disadvantage of this implementation is that clock nodes
are toggling during idle conditions. Due to low level of activity in static blocks, data enabling does not
offer a large power saving advantage since clock nodes consume majority of the power. In high-frequency
design, where aggressive circuit techniques such as domino logic are employed, this technique offers a
great deal of power saving. In domino logic, data/non-clocked node activity factors are relatively high.
In these cases, the “data enable” signal can be used to avoid evaluation of the first stage of a domino
block or to set data inputs to a default state such that the domino gate does not discharge. It is also
important to note that clock enabling (gating) for a block will save both clock and data power since the
block will be turned off and there is no activity within the block unlike the data enabling.
Datapath circuits are the second highest power consuming category of circuits, after clock in modern
high-performance designs. In such designs, datapath including register files fall in critical paths and hence
they are custom designed (that is, carefully designed manually by expert designers). These designs involve
manual tweaking of transistors and can lead to over-sizing of the devices, which become excessive power
wasters. In addition, the choice of circuit family used, e.g., static versus domino can also influence the
circuit’s power consumption. To design a power-efficient circuit, the power-delay curve approach can be
of great help, as described in the “Need for Power Estimation Tools” section (Fig. 14.6). CAD tools that
enable a circuit family of this kind and design exploration for custom circuits can thus have a significant
impact at full-chip level.
In the CPU arena, a lot of circuits, which are performance critical, get implemented as domino circuits.
Wide datapaths such as adders, incrementors, and shifters are implemented in domino. In that case, specific
optimizations on individual circuits can be done to reduce power. Consider an example of a domino
mulitplexer, which usually appear in shifters, as shown in Fig. 14.13.
In this circuit, at least one of SelA, SelB, and SelC is high every cycle. The data inputs A#, B#, C# are
mostly high (A, B, C have very low signal probability). In this situation, all the capacitances associated
with the data nodes toggle almost every cycle. This total capacitance is almost three times that associated
with the clocked nodes. Consequently, when the polarity of the data inputs is changed, as shown on the
right, large power savings are seen.
© 2002 by CRC Press LLC
Enable
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Data
enable
FF
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