U. Glaeser

The supply and substrate noise generated by the on-chip and off-chip sources is highly data dependent
and can have a wide range of frequency components that include low frequencies. Substrate noise tends
not to have as large low-frequency components as possible for supply noise since no significant “DC”
drops develop between the substrate and the supply voltages. Under worst-case conditions, DLLs and
PLLs may experience as much as 500 mV of supply noise and 250 mV of substrate noise with a nominal
2.5 V supply. The actual level of substrate noise depends on the nature of the substrate used by the IC
process. To reduce the risk of latch-up, many IC processes use lightly doped epitaxy on the same type
heavily doped substrate. These substrates tend to transmit substrate noise across large distances on the
chip, which make it difficult to eliminate through guard rings and frequent substrate taps.
Supply and substrate noise affect DLLs and PLLs differently. They affect a DLL by causing delay shifts
in the delay line output, which lead to fixed phase shifts that persist until the noise pulses subside or the
DLL can correct the delay error, at a rate limited by its bandwidth (proportional to ω REF/ω N cycles). They
affect a PLL by causing frequency shifts in the oscillator output, which lead to phase shifts that accumulate
for many cycles until the noise pulses subside or the PLL can correct the frequency error, at a rate limited
by its bandwidth (proportional to ω REF /ω N cycles). Because the phase error caused by period shifts in PLLs
accumulate over many cycles, unlike the delay shifts in DLLs, the tracking jitter for PLLs that results from
supply and substrate noise can be several times larger than the tracking jitter for DLLs; however, due to
the added jitter from on-chip clock distribution networks, which typically have poor supply and substrate
noise rejection, the observable difference is typically less than a factor of 2 for well designed DLLs and
PLLs.
DLL Supply/Substrate Noise Response
More insight can be gained into the noise response of DLLs and PLLs by considering how much jitter is
produced as a function of frequency for supply and substrate noise. Figure 10.12 shows the output jitter
sensitivity to input jitter for a DLL with a log-log plot of the absolute output jitter magnitude normalized
to the absolute input jitter magnitude as a function of the input jitter frequency. Because the DLL simply
delays the input signal, the jitter at the input is simply replicated with the same magnitude at the DLL
output. For the same reason, the tracking jitter sensitivity to input jitter is very small at most frequencies;
however, when the input jitter frequency approaches one half of the inverse of the delay line delay, the
output jitter becomes 180° out-of-phase with respect to the input jitter and the observed tracking jitter
can be twice the input jitter.
Figure 10.13 shows the output jitter sensitivity to sine-wave supply or substrate noise for a DLL with
a log–log plot of the absolute output jitter magnitude as a function of the noise frequency. With the
input jitter free, this absolute output jitter is equivalent to the tracking jitter. Also, since the DLL simply
delays the input signal, the absolute output jitter is equivalent to the period jitter. This plot shows that
the normalized jitter magnitude decreases at 20 dB per decade for decreases in the noise frequency below
the loop bandwidth and is constant at one for noise frequencies above the loop bandwidth. This behavior
results since the DLL acts as a low-pass filter to changes in its input period or, equivalently, to noise
induced changes in its delay line delay. Thus, the jitter or delay error is the difference between the noise
induced delay error and a low-pass filtered version of the delay error, leading to a high-pass noise response.
FIGURE 10.12 DLL output jitter sensitivity to input jitter.
© 2002 by CRC Press LLC
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