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U. Glaeser

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FIGURE 2.85 Main process steps of ITOX-SIMOX.<br />

SIMOX Substrates<br />

For SIMOX substrates, the buried oxide (BOX) layer is formed by the implantation of a large quantity<br />

of oxygen ions at energies of about 200 keV followed by annealing at high temperatures above 1300°C,<br />

as shown in Fig. 2.85 [4]. Because the amount of oxygen implanted and the implantation energy are<br />

controlled electronically with high accuracy, there is excellent control of the uniformity of the thickness<br />

of the SOI layer and the BOX layer. A substrate obtained by high-dose oxygen implantation in the order<br />

of 10 18 cm 2 is called a high-dose SIMOX substrate and has a BOX layer thickness of about 400–500 nm.<br />

The presence of 10 8 cm 2 or more dislocation density in the SOI layer and the long period of time required<br />

for the high-dose oxygen ion implantation create problems with respect to the quality of the SOI layer<br />

and the cost and mass producibility of the substrate. On the other hand, it has been discovered that if<br />

the oxygen ion implantation dose is lowered to about 4 × 10 17 cm 2 , there are dose regions in which the<br />

dislocation density is reduced to below 300 cm 2 , resulting in high quality of the SOI layer and lower<br />

substrate cost [12]. Such a substrate is referred to as a low-dose SIMOX substrate. However, the BOX<br />

layer of this substrate is thin (about 90 nm), making it necessary to reduce the number of pinholes and<br />

other defects in the BOX layer. In later studies, it was found that a further high-temperature oxidation<br />

at over 1300°C after high-temperature annealing results in the formation of a thermal oxide layer at<br />

the interface between the SOI layer and BOX layer at the same time as the oxidation of the SOI layer<br />

surface [13]. Typically, the BOX layer thickness is increased by about 40 nm. A substrate produced with<br />

this internal oxidation processing is referred to as an ITOX-SIMOX substrate. In this way, an SOI layer<br />

can be formed over an oxide layer of high quality, even on SIMOX substrates formed by oxygen ion<br />

implantation.<br />

ELTRAN Substrates<br />

Although thin-film SOI substrates for fine CMOS devices are categorized as either SIMOX substrates or<br />

wafer bonded substrates, as shown in Fig. 2.84. ELTRAN substrates are classified as BESOI (Bond and<br />

Etch-back SOI) substrates, a subdivision of the bonded substrate category. The BESOI substrate is<br />

produced by the growth of a two-layer structure that consists of the final layer that remains on the DW<br />

as the SOI layer and a layer that has a high etching speed by epitaxial growth followed by the formation<br />

of a thermal oxide layer on the surface and subsequent bonding to the HW. After that, most of the<br />

substrate is removed from the backside of the DW by grinding and polishing. Finally, the difference in<br />

etching speed is used to leave an SOI layer of good uniformity. The fabrication process for an SOI substrate<br />

produced by the ELTRAN method is shown in Fig. 2.86 [14]. First, a porous Si layer that comprises two<br />

layers of different porosities is formed by anodization near the surface of the Si substrate on which the<br />

devices are formed (DW). After smoothening of the wafer surface by annealing in hydrogen to move the<br />

surface Si atoms, the layer that is to remain as the SOI layer is formed by epitaxial growth. After forming<br />

the layer that is to become the buried oxide layer by oxidation, the DW is bonded to the HW. Next, a<br />

water jet is used to separate the DW and HW at the boundary of the two-layer porous Si layer structure.<br />

Finally, the porous Si layer is removed by selective chemical etching of the Si layer, hydrogen annealing<br />

© 2002 by CRC Press LLC<br />

O + ions<br />

Si Substrate<br />

Thermal Oxide<br />

SOI (320 nm)<br />

BOX (80 nm)<br />

Si Substrate<br />

O + Ions implantation High temperature annealing<br />

>1300 C<br />

Thermal Oxide<br />

SOI (62 nm)<br />

BOX (120 nm)<br />

Si Substrate<br />

Internal thermal oxidation<br />

>1300 C

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