U. Glaeser

FIGURE 11.4 Current-mode CMOS quaternary-to-binary decoder.
loads of 100 pF that use nominal 3 mA incremental currents are realized with: (1) no bias current, and
(2) a 50 µ A bias current. The encoder and decoder circuits operated exactly as predicted. Propagation
delay of binary/quaternary encoder-decoder circuits has been defined as the 50–50% delay time from
the incidence of the simultaneous binary encoder inputs to the generation of the last binary decoder
output. Worst-case propagation delay is experienced when the encoder output changes three full increments
of output current. Propagation delays of our current-mode, encoder-decoder circuit pairs have
been measured with the encoder output and decoder input package pins wired together on a breadboard.
Thus, the encoder circuit drives off-chip, through the package, to a board, back through the package,
on-chip, and lastly the decoder circuit. Typical values of CMOS-voltage-input-to-CMOS-voltage-output
propagation delay exhibited by the small-current (intended for on-chip use) encoder-decoder pairs
without and with bias current driving off-chip are about 375 and 275 ns, respectively. Because the largecurrent,
encoder-decoder circuits were designed to drive PC board loads of 100 pF, we have examined
the large-current, encoder-decoder circuit pairs loaded as outlined previously with an additional capacitance
load of nominal value 100 pF connected from the I/O node to ground. Under this loading
condition, typical values of delay exhibited by the large-current encoder-decoder circuits without and
with bias current are about 48 and 30 ns, respectively. Although the use of large signaling currents may
not be attractive to many designers, the option is available and may be of value in some situations.
One might use encoder/decoder circuits to increase the information on a signal line. Current summing
at a node is a “free” computation that may be exploited in circuits that realize threshold logic functions
as we will see in the next section where we summarize the quaternary threshold logic full adder.
Current-Mode CMOS Quaternary Threshold Logic Full Adder
Some operations in digital signal processing and computing are more amenable than others to implementation
with quaternary threshold logic. For example, by using the summing of logical currents, adding
and counting may be efficiently implemented. The quaternary threshold logic full adder (QFA) adds
the values of two quaternary inputs A and B,
and the value of a binary carry input,
© 2002 by CRC Press LLC
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, and produces a