U. Glaeser

FIGURE 2.45 Example decomposed BDD.
FIGURE 2.46 Elimination by composition.
MPL has superior characteristics compared to monolithic PTL, especially in terms of delay, because
the depth of sub-BDDs in a multilevel BDD is much less than that of a monolithic BDD. Empirically,
the delay can be reduced by a factor of 2 compared to the monolithic PTL [11]. In addition, MPL is
effective in simplifying the circuit, because more sub-graphs than in the monolithic BDD can be shared
by extraction.
The other method is to directly build hierarchical BDDs simultaneously, without constructing a
monolithic BDD [9]. Such a BDD is also called a decomposed BDD. Figure 2.45 shows an example. The
decomposed BDD is constructed from input to output according to the structure of the circuit corresponding
to the logic function. During the construction, the size and depth of the BDD is monitored
and if either value is over a limit, BDD construction is stopped and a new intermediate variable that
points to the output of the BDD is introduced. In this example, x, y, and z are the intermediate variables.
BDD construction is then restarted and the decomposed BDD is obtained by repeating this process. Here,
a point where a new intermediate variable is introduced is called a decomposed point.
The decomposed BDD has a superior characteristic in that for certain logic functions, such as a
multiplier, which cannot be constructed in a practical size from a monolithic BDD [23], it is possible to
build a decomposed BDD and synthesize a pass-transistor circuit. Therefore, the decomposed BDD is
essential for a practical PTL synthesis, and many methods based on the decomposed BDD have been
proposed [12,13,34]. Another merit of the decomposed BDD is that by changing the decomposed points,
the characteristics of the synthesized MPL can be flexibly controlled [9,12,13]. However, the decomposed
BDD has a drawback, in that canonicity is not guaranteed because of the freedom in selecting decomposed
points. This means that the synthesized result depends on the quality of the input logic description, or
in other words, it may contain some redundancy. For this reason, in a decomposed BDD, sub-BDDs are
simplified by several methods [9,12] such as elimination, shown in Fig. 2.46. Elimination removes the
redundancy by composition of two or more sub-BDDs. Moreover, as with multilevel CMOS logic
synthesis, BDD simplification based on “don’t care” conditions, such as satisfiability don’t care (SDC)
and observability don’t care (ODC), can be applied, as shown in Fig. 2.47 [12,29,30].
PTL Cell
In practical PTL synthesis several cells, each of which packs one or more selectors, inverters, and a
pull-up pMOS transistor, are used, although PTL circuits can be synthesized with only two cells,
namely a selector and an inverter. These packed cells of one or more selectors are effective not only
© 2002 by CRC Press LLC
Out = AB + CD + EF
A x
B
C
D y
E
F z
(a) Logic function and decomposed points
0
B
A
X
1
Out
A
Out
X
0
y = CD
C
D
1
z = EF
E
F
0
Out = x + y + z
0 1
(b) Decomposed BDD using x, y, z
composition
z
y
x
Out
0 1 0 1
A
1
0
x = AB
A
B
1