U. Glaeser

FIGURE 42.5 Polyphase filter structures for interpolation and decimation.
T s
FIGURE 42.6 Variable rate interpolation.
Given the coefficients of an FIR decimation or interpolation filter, the structure of choice for the realization
of a decimate by D or an interpolate by D filter is the polyphase structure [12] shown in Fig. 42.5.
The attractiveness of this structure is in the fact that the filter is always operated at the lower sampling
frequency.
N
In many cases it is desirable to resample the signal by a power of 2 . In which case N decimate
(interpolate) by two stages can be cascaded one after the other. Each decimator will consist of a halfband
filter followed by a decimator. The halfband filter could be realized using the polyphase structure to
simplify its implementation. Moreover, these filters are typically very small consisting of anywhere from
7 to 15 taps depending on the specified stopband attenuation and the size of the transition band. Their
implementation can be simplified by exploiting the fact that close to half of the coefficients are zero and
the remainder are symmetric about the main tap due to the linear phase characteristics of the halfband
filter. Finally, since these are fixed-coefficient filters, they can be realized using CSD
coefficients [13].
It is interesting to note that for the special case of a decimate (interpolate) by 2N,
it is possible to reuse
the same hardware element and simply recirculate the data through it. In this architecture, the filter is
run at the highest data sampling rate. The first pass through the filter will use up 1/2 of its computational
resources, the second pass will use up 1/4 of the resources, and so on [14]. Although conceptually
attractive, the clock generation circuit for such an architecture is quite critical and complex and this
approach looses its appeal for recirculating factors greater than 3 or 4.
In cases where the oversampling ratio is large (e.g., narrowband signal) an alternative approach using
a cascaded integrator-comb (CIC) structure can be used to implement a multiplierless decimator. The
interested reader is referred to [15] for a brief overview of a CIC ASIC.
The continuously variable decimator block shown in Fig. 42.2 can resample the input signal by any
factor α in the range of 2–4. The operation of this block is equivalent to that shown in Fig. 42.6, where
the input data x(
n),
originally sampled at 1/ Ts
is resampled to produce an output sequence y(
n)
sampled
at 1/ Ti.
The entire operation is performed digitally.
To better understand the operation of this block, let us define the variable µ k,
to be the time difference
between the output sample y(
k) and the most recent input sample x1. The job of the variable rate
interpolator is to weight the adjacent input samples (…, x0, x1,…), based on the ratio µ k/Ts, and add the
weighted input samples to obtain the value of the output sample, y(k). Mathematically, a number of
interpolation schemes can perform the desired operation; however, many of them, such as sinc-based interpolation,
require excessive computational resources for a practical hardware implementation. For real-time
© 2002 by CRC Press LLC
x(n)
Decimator
Structure
α
T i
x(n)
h 0 , h U , h 2U , ...
h 1 , h U +1 , h 2U +1 , ...
h U -1 , h 2U -1 , h 3U +1 ...
T s
h 0 , h D , h 2D , ...
h 1 , h D +1 , h 2D +1 , ...
Interpolator
Structure
y(n)
h D -1 , h 2D -1 , h 3D -1 , ...
DAC
Continuous
time filter
y(n)