U. Glaeser

k + 1, etc. Extending to a third stage:
© 2002 by CRC Press LLC
c k+3 = g k+2 + p k+2c k+2
= gk+2 + pk+2 ( gk+1 + pk+1g k + pk+1p kck) = g k+2 + p k+2 g k+1 + p k+2 p k+1 g k + p k+2 p k+1p kc k
(9.8)
Although it would be possible to continue this process indefinitely, each additional stage increases the
fan-in (i.e., the number of inputs) of the logic gates. Four inputs (as required to implement Eq. (9.8))
is frequently the maximum number of inputs per gate for current technologies. To continue the process,
block generate and block propagate signals are defined over four bit blocks (stages k to k + 3), g k:k+3 and
p k:k+3, respectively:
and
g k:k+3 = g k+3 + p k+3 g k+2 + p k+3 p k+2 g k+1 + p k+3 p k+2 p k+1 g k
p k:k+3 = p k+3 p k+2 p k+1 p k
Equation (9.6) can be expressed in terms of the 4-bit block generate and propagate signals:
c k+4 = g k:k+3 + p k:k+3 c k
(9.9)
(9.10)
(9.11)
Thus, the carry out from a 4-bit wide block can be computed in only four gate delays (the first to compute
pi and gi for i = k through k + 3, the second to evaluate pk:k+3, the second and third to evaluate gk:k+3, and
the third and fourth to evaluate ck+4 using Eq. (9.11)).
An n-bit carry lookahead adder requires ( n – 1)/
( r – 1)
lookahead blocks, where r is the width
of the block. A 4-bit lookahead block is a direct implementation of Eqs. (9.6)–(9.10), with 14 logic gates.
In general, an r-bit lookahead block requires (3r + r 2 1
-- ) logic gates. The Manchester carry chain [3] is an
2
alternative switch-based technique for the implementation of the lookahead block.
Figure 9.5 shows the interconnection of 16 adders and five lookahead logic blocks to realize a 16-bit
carry lookahead adder. The sequence of events, which occur during an add operation, is as follows: (1)
apply A, B, and carry in signals, (2) each adder computes P and G, (3) first level lookahead logic computes
the 4-bit propagate and generate signals, (4) second level lookahead logic computes c4, c8, and c12, (5)
first level lookahead logic computes the individual carries, and (6) each adder computes the sum outputs.
This process may be extended to larger adders by subdividing the large adder into 16-bit blocks and
using additional levels of carry lookahead (a 64-bit adder requires three levels).
The delay of carry lookahead adders is evaluated by recognizing that an adder with a single level of
carry lookahead (for 4-bit words) has six gate delays, and that each additional level of lookahead increases
the maximum word size by a factor of four and adds four gate delays. More generally [4, pp. 83–88], the
number of lookahead levels for an n-bit adder is logrn where r is the maximum number of inputs
per gate. Since an r-bit carry lookahead adder has six gate delays and there are four additional gate delays
per carry lookahead level after the first,
DELAYCLA = 2 + 4 logrn (9.12)
The complexity of an n-bit carry lookahead adder implemented with r-bit lookahead blocks is n
modified full adders (each of which requires eight gates) and ( n – 1)/
( r – 1)
lookahead logic blocks
[each of which requires (3r + r 2 1
-- ) gates].
2
GATESCLA = 8n + (3r + r 2 1
-- ) n – 1
(9.13)
2
----------r
– 1