U. Glaeser

difficult to identify for overcurrent detection). Dynamic fault models require more test patterns than
static fault models, but the effort for test pattern generation for dynamic fault models is tolerable. The
highest effort in test pattern generation was spent for getting robust single input transition test patterns
(Table 45.3) as expected. The time required for mixed-level test pattern generation is almost equal to the
functional identical circuits described exclusively on the gate-level.
A further compaction of the test set, in addition to the compaction (described in the subsection on
“Merging of Test Pattern Pairs”) leading to a minimal test set, is not performed because long pattern
sequences computed for transition fault models are difficult to compress with reordering methods as
proposed in [2] for stuck-at pattern sets. With the use of an advanced fault simulator, which includes timing
conditions such as FEHSIM [39,42], a further compaction of patterns is possible since MILEF performs a
worst-case robustness check as described in the subsection on “Robustness Check for Pattern Pairs.”
45.3 The Fogbuster Algorithm for Synchronous Circuits
To also handle mixed-level sequential circuits without or with a partial scan path, the sequential test
generation system SEMILET (sequential mixed-level test generator) was developed as an extension to
MILEF. To improve shortcomings of the state-of-the-art test generators such as HITEC [43] and GENTEST
[44], the FOGBUSTER (forward propagation backward justification sequential test generator) algorithm
was developed.
The only algorithm that uses exclusively forward time processing is the FASTEST approach [45]. The
shortcomings of this algorithm are:
• The circuit is copied as often as needed for test generation, so it is very memory consuming.
• The test generation algorithm, in general, needs a large decision tree for fault excitation.
In this section, the FOGBUSTER algorithm for test generation for synchronous sequential circuit and
the sequential test generator SEMILET, which makes use of this algorithm are described.
This section is organized as follows: Synchronous circuits that can be handled by our ATPG are
characterized in subsection “Circuits.” The main differences of FOGBUSTER and the BACK-algorithm
are pointed out in subsection “General Approach in Comparison with Other Algorithms.” The section
“Test Generation Technique” describes FOGBUSTER, and subsection “Fault Propagation and Propagation
Justification” gives a detailed description of the forward propagation technique. A solution for the
over specification problem is presented in next subsection and finally, in next two subsections, the test
generator SEMILET using the FOGBUSTER algorithm is described. Experimental results from the
ISCAS ’89 benchmark circuits [46] are given in subsection “Experimental Results.”
Circuits
FOGBUSTER and SEMILET can handle a superset of synchronous sequential circuits that HITEC [43]
and GENTEST [44] accept. These circuits have to match the following characteristics:
• All feedback loops include at least one storage element.
• All storage elements have a clock input that is connected to one global clock signal, one data input,
and one noninverting data output. It is assumed that the storage elements are master-slave flipflops,
or edge-triggered D-flip-flops.
• Global set and/or reset signals that affect all storage elements are allowed. The test generator can
take advantage of them.
• The circuit may consist of primitive (AND, NAND, OR, NOR) and combinational complex gates.
The restriction concerning the types of storage elements seems to be severe at first, but if the design
consists of storage elements with a local set and/or reset possibility or with multiple clocking phases,
© 2002 by CRC Press LLC