U. Glaeser

References
1. D. Kahng and M. M. Atalla, “Silicon-silicon dioxide field induced durface devices,” IRE Solid-State
Device Res. Conf., 1960.
2. SIA, EECA, EIAJ, KSIA, and TSIA, “International Technology Road Map for Semiconductors,” in
1999 edition.
3. R. H. Dennard, F. H. Gaensslen, H.-N., Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of
ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, SC-9,
pp. 256–268, 1974.
4. M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, “Sub-50 nm gate length n-
MOSFETs with 10 nm phosphorus source and drain junctions,” IEDM Tech. Dig., pp. 119–122,
December, 1993.
5. H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, “Tunnelling
gate oxide approach to ultra-high current drive in small-geometry MOSFETs,” IEDM Tech., pp. 593–
596, 1994.
6. C. Fiegna, H. Iwai, T. Wada, M. Saito, E. Sangiorgi, and B. Ricco, “A new scaling methodology for
the 0.1–0.025 µm MOSFET,” Symp. on VLSI Tech., pp. 33–34, 1993.
7. T. Ohguro, K. Yamada, N. Sugiyama, K. Usuda, Y. Akasaka, T. Yoshitomi, C. Fiegna, M. Ono, M.
Saito, and H. Iwai, “Tenth micron P-MOSFET’s with ultra-thin epitaxial channel layer grown by
ultra-high vacuum CVD,” IEDM Tech. Dig., pp. 433–436, December, 1993.
8. T. Ohguro, N. Sugiyama, K. Imai, K. Usuda, M. Saito, T. Yoshitomi, M. Ono, H. S. Momose, and
H. Iwai, “The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 µm epitaxial Si channel
n-MOSFETs grown by UHV-CVD,” Symp. on VLSI Tech., pp. 21–22, 1995.
9. T. Yoshitomi, M. Saito, T. Ohguro, M. Ono, H. S. Momose, and H. Iwai, “Silicided silicon-sidewall
source and drain (S4D) structure for high-performance 75-nm gate length p-MOSFETs,” Symp. on
VLSI Tech., pp. 11–12, 1995.
10. T. Morimoto, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, H. Okano, I. Katakabe, H. Nakajima,
M. Tsuchiaki, M. Ono, Y. Katsumata, and H. Iwai, “A NiSi salicide technology for advanced logic
devices,” IEDM Tech. Dig., pp. 653–656, December, 1991.
11. Semiconductor Industry Association, “National Technology Roadmap for Semiconductors,” 1994,
1997 editions.
12. SIA, EECA, EIAJ, KSIA, and TSIA, “International Technology Road Map for Semiconductors,” in
1998 update, 1999 edition, 2000 update.
13. http://www.intel.com.
14. T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, “Scaling challenges
and device design requirements for high performance sub-50 nm gate length planar CMOS transistors,”
Symp. on VLSI Tech., Dig. Tech., pp. 174–175, June, 2000.
15. R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani,
A. Murthy, and G. Dewey, “30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and
1.7 ps p-MOS gate delays,” IEDM Tech. Dig., pp. 45–49, December, 2000.
16. E. Leobandung, E. Barth, M. Sherony, S.-H. Lo, R. Schulz, W. Chu, M. Khare, D. Sadana, D. Schepis,
R. Bolam, J. Sleight, F. White, F. Assaderaghi, D. Moy, G. Biery, R. Goldblatt, T.-C. Chen, B. Davari,
and G. Shahidi, “High Performance 0,18 µm SOI CMOS Technology,” IEDM Tech. Dig., pp. 679–682,
December, 1999.
17. T. Ghani, S. Ahtned, P. Aminzadeh, J. Bielefeld, P. Charvat, C. Chu, M. Harper, P. Jacob, C. Jan,
J. Kavalieros, C. Kenyon, R. Nagisetty, P. Packan, J. Sebastian, M. Taylor, J. Tsai, S. Tyagi, S. Yang,
and M. Bohr, “100 nm gate length high performance/low power CMOS transistor structure,” IEDM
Tech. Dig., pp. 415–418, December, 1999.
18. G. Timp, J. I. Bude, K. K. Bourdelle, J. Garno, A. Ghetti, H. Gossmann, M. Green, G. Forsyth, Y. Kim,
R. Kleiman, F. Klemens, A. Komblit, C. Lochstampfor, W. Mansfield, S. Moccio, T. Sorsch, D. M. Tennant,
W. Timp, and R. Tung, “The ballistic nano-transistor,” IEDM Tech. Dig., pp. 55–58, December, 1999.
© 2002 by CRC Press LLC