U. Glaeser

Frequency (GHz)
FIGURE 10.23 Frequency sensitivity to supply voltage for a ring oscillator with differential delay elements and a
replica-feedback current source bias circuit in a 0.5 µm N-well CMOS process.
the clock period. Thus, the requirement for a 50% duty cycle can be satisfied without operating the PLL
at twice the chip operating frequency, if a single-ended CMOS output with 50% duty cycle can be obtained
from a differential output signal. This conversion can be accomplished using an amplifier circuit that
has a wide bandwidth and is balanced around the common-mode level expected at the inputs so that
the opposing differential input transitions have roughly equal delay to the output. Such circuits will
generate a near 50% duty cycle output without dividing by two provided that device matching is not a
problem; however, on-wafer device mismatches for nominally identical devices will tend to unbalance
the circuit and establish a minimum signal input and internal bias voltage level below which significant
duty-cycle conversion errors may result. In addition, as the device channel lengths are reduced, device
mismatches will increase. Therefore, using a balanced differential-to-single-ended converter circuit instead
of a divider can relax the design constraints on the VCO for high-frequency designs but must be used with
caution because of potential device mismatches.
Phase Detectors
The phase detector detects the phase difference between the reference input and the feedback signal of a
DLL or PLL. Several types of phase detectors can be used, each of which will allow the loop achieve a different
phase relationship once in lock. An XOR or mixer can be used as a phase detector to achieve a quadrature
lock on input signals with a 50% duty cycle. The UP and DN outputs are complementary, and, once in
lock, each will generate a 50% duty cycle signal at twice the reference frequency. The 50% duty cycle will
cause the UP and DN currents to cancel out leaving the control voltage unchanged. An edge-triggered SR
latch can be used as the phase detector for an inverted lock. The UP and DN outputs are also complementary,
and, once in lock, each will generate a 50% duty cycle signal at the reference frequency. If differential inputs
are available, an inverted lock can be easily interchanged with an in-phase lock. A sampling flip-flop can
be used to sample the reference clock as the phase detector in a digital feedback loop, where the flip-flop
is used to match the input delay for digital inputs also sampled by identical flip-flops. The output state of
the flip-flop will indicate if the feedback clock is early or late. Finally, a phase-frequency detector (PFD)
can be used as a phase detector to achieve an in-phase lock. PFDs are commonly based on two SR latches
or two D flip-flops. They have the property that only UP pulses are generated if the frequency is too low,
only DN pulses are generated if the frequency is too high, and to first order, no UP or DN pulses are
generated once in lock. Because of this property, PLLs using PFDs will slew their control voltage with, on
© 2002 by CRC Press LLC
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