U. Glaeser

FIGURE 2.11 (a) The general structure of a Pseudo-NMOS logic; (b) Pseudo-NMOS realization of a 2-input NAND
gate; (c) Pseudo-NMOS realization of a 2-input NOR gate; (d) Pseudo-NMOS realization of the logic function Y =
(ABC + D)′.
The pull-down network realizes the logic function and a PMOS with grounded gate presents the load
device, as shown in Fig. 2.11(a). The pseudo-NMOS logic style results in a substantial reduction in gate
complexity, by reducing the number of transistors required to realize the logic function by almost half.
The speed of the pseudo-NMOS circuit is faster than that of static CMOS realization because of smaller
parasitic capacitance. One of the main disadvantages of this design style is the increased static power
dissipation. This is due to the fact that, at steady state when the output is 0, pseudo-NMOS circuits
provide dc current path from V DD to ground. Figure 2.11(b) shows the realization of a 2-input NAND
gate using pseudo-NMOS logic. When the inputs A = 0 and B = 0, both the transistors in the pull-down
network will be OFF and the output will be a logic 1. When A = 0 and B = 1, or A = 1 and B = 0, the
pull-down network again will be OFF and the output will be logic 1. When A = 1 and B = 1, both
transistors in the pull-down network are ON and the output will be a logic 0, which is the expected
result of a NAND gate. Figure 2.11(c) illustrates the pseudo-NMOS realization of a 2-input NOR gate.
Another example for the pseudo-NMOS logic realization is given in Fig. 2.11(d). This circuit realizes
the function Y = (ABC + D)′, and the operation of this logic circuitry can also be explained in a manner
explained above.
Pass Transistor/Transmission Gate Logic
In all the circuits we have discussed so far, the outputs are obtained by closing either the pull-up network
to VDD or the pull-down network to ground. The inputs are used essentially to control the condition
of the pull-up and the pull-down networks. One may design circuits in which the input signals in addition
to VDD and VSS are steered to output, depending on the logic function being realized. Pass transistor
logic implements a logic gate as a simple switch network. The pass transistor design methodology has
the advantage of being simple and fast. Complex CMOS combinational logic functions can be implemented
with minimal number of transistors. This results in reduced parasitic capacitance and hence
faster circuits. As a pass transistor design example, Fig. 2.12 shows a Boolean function unit realized using
© 2002 by CRC Press LLC