U. Glaeser

FIGURE 15.16 Triple-V th CMOS/SMOX circuit [33].
To make different V th devices, some steps of fabrication process are added. A fabrication process and the
effects of dual V th MOS circuits are discussed in [32].
Figure 15.16 shows an example of a dual V th circuit with a high-V th power switch [33]. The high-V th
transistor is used to cut off subthreshold leakage current. In the logic circuit, low-V th devices and
medium-V th devices are used to make a dual-V th circuit system. In a 16-bit ripple-carry adder, the activeleakage
current is reduced to one-third that of the all low-V th adder. Two design approaches are used
for dual-V th circuit. One approach designs the entire device using low-V th transistors at first. If the delay
of a circuit path is faster than the required clock period, the circuit is replaced to a high-V th transistor.
The other approach allows all of circuits to be designed as high-V th transistors at first. If a circuit path
cannot operate at a required clock speed, the circuit is replaced to a low-V th transistor. The synthesis
algorithms are examined in [34,35].
15.5 Clock Distribution Management
Conditional Clocking
A global clock network consumes 32% of the power in an Alpha 21264 processor [36]. This power is
eliminated when clock distribution is suspended by gating during the idle state.
The operating power is also reduced with the conditional clocks, which deliver clock signals only to
active modules. The Alpha 21264 uses conditional clocking in the data path as shown in Fig. 15.17. For
instance, the control logic asserts the ADD CLK ENABLE signal when a floating-point addition is executed.
The enable pulse propagates through latches to drive the AND gates. Other units are disabled while the
adder is executed. When a datapath is not needed, the enable signal is negated, and the clock to that path
is halted. The clock network reduces the power to 25% of the unconditional case when no floating-point
instruction is executed.
Multiple Frequency Clock
Multiple frequency clocks are used in the Super-H microprocessor [37]. This microprocessor has three
kinds of clocks: I-clock for the internal main modules, B-clock for the bus lines, and P-clock for the
peripheral circuits. Maximum frequencies of each clock are 200, 100, and 50 MHz, respectively. Compared
to a 200 MHz single-clock design, it reduces the distribution power by 23%.
© 2002 by CRC Press LLC
SL
V dd
High-V th power switch MOSFET
(V th - 0.4 V)
Virtual V dd
IN Low-VthCMOS logic
OUT
(|Vth | 0.1 V)
Med-V th CMOS logic
(|V th | 0.2 V)