U. Glaeser

Pass-Transistor Logic Styles
Various PTL circuits, static or dynamic, can be implemented using two fundamental design styles: the
style that uses NMOS pass-transistors only and the style that uses both NMOS and PMOS passtransistors.
Within each of these two styles, there is a further differentiation based on realization of the
output stage.
NMOS Pass-Transistor Logic
Complementary pass-transistor logic (CPL), introduced in [3], consists of an NMOS pass-transistor
network, and CMOS output inverters. The circuit function is implemented as a tree consisting of pulldown
and pull-up branches. Since the “high” level at the pass-transistor outputs experiences degradation
by the threshold voltage drop of NMOS transistors, the outputs are restored to full-swing by CMOS
inverters, Fig. 2.56. Conventional CPL [3] uses restoration option (a). It is suitable for driving large
output loads because the output load is decoupled from the internal nodes of the PTL network. Subfamily
based on restoration option (b) is called differential cascode voltage switch with the pass-gate (DCVSPG),
and it is good in driving smaller loads. Restoration option (c) is associated with the logic family called
swing-restored pass-transistor logic (SRPL) [4]. Another variation of (b), which employs level restoring
circuit shown in Fig. 2.56(d), was introduced in [5] in a logic family called power saved pass-transistor
logic (PSPL). Compared to conventional CPL, this technique compromises circuit speed for smaller
power consumption, resulting in worse energy-delay product.
Sizing of pass-transistors is an important issue. As discussed in [5], the NMOS transistors closer
to the output have smaller size than the transistors farther away from the output because the transistors
closer to the output pass smaller swing “high” signals due to the voltage drop across the transistors
away from the output. However, this technique has to be carefully applied because small output
transistors might not be able to provide sufficient driving strength at the output if the output load
is large.
The LEAP pass-transistor library [6], uses two level restoring circuits, one for driving small loads,
Fig. 2.57(a), and another for driving very large loads, Fig. 2.58(b). This level restoring technique
decouples the true and complementary outputs in conventional CPL (dashed PMOS transistors in
Fig. 2.56(a)).
CPL has traditionally been applied to the implementation of arithmetic building blocks [3,6–9], and
it has been shown to result in high-speed operation due to its low input capacitance and reduced transistor
count. Also, this logic family has smaller noise margins compared to the conventional CMOS.
FIGURE 2.56 NMOS pass-transistor subfamilies: (a) CPL, (b) DCVSPG, (c) SRPL, (d) PSPL.
FIGURE 2.57 The output inverters in LEAP library of driving (a) large and (b) small output capacitance.
© 2002 by CRC Press LLC
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