U. Glaeser

FIGURE 2.15 A general model of a sequential network.
Sequential CMOS Logic Circuits
As mentioned earlier, in combinational logic circuits, the outputs are a logic combination of the current
input signals. In sequential logic circuits the outputs depend not only on the current values of the inputs,
but also on the preceding input values. Therefore, a sequential logic circuit must remember information
about its past state. Figure 2.15 shows the schematic of a synchronous sequential logic circuit. The circuit
consists of a combinational logic circuit, which accepts inputs X and Y1 and produces outputs Z and Y2. The output Y2 is stored in the memory element as a state variable. The number of bits in the state
variable decides the number of available states, and for this reason a sequential circuit is also called a
finite state machine. The memory element can be realized using level-triggered latches or edge triggered
flip-flops.
For a VLSI circuit designer, a number of different latches and flip-flops are available for the design
of the memory element of a sequential circuit. Figure 2.16(a) shows the diagram of a CMOS positive
level sensitive D latch realized using transmission gates and inverters and its switch level equivalent
circuits for CLK = 0 and CLK = 1. It has a data input D and a clock input CLK. Q is the output and
the complement of the output Q′ is also available. When CLK = 0, the transmission gate in the inverter
loop will be closed and the transmission gate next to the data input will be open. This establishes a
feedback path around the inverter pair and this feedback loop is isolated from the input D as shown
in Fig. 2.16(a). This causes the current value of Q (and hence Q ′) to be stored in the inverter loop.
When the clock input CLK = 1, the transmission gate in the inverter loop will be open and the transmission
gate close to the input will be closed, as shown in Fig. 2.16(a). Now the output Q = D, and the
data is accepted continuously. That is, any change at the input is reflected at the output after a nominal
delay. By inverting the clocking signals to the transmission gates a negative level sensitive latch can be
realized.
A negative level sensitive latch and a positive level sensitive latch may be combined to form an edge
triggered flip-flop. Figure 2.16(b) shows the circuit diagram of a CMOS positive edge triggered D flipflop.
The first latch, which is the negative level sensitive latch, is called the master and the second latch
(positive level sensitive latch) is called the slave. The electrical equivalent circuits for the CMOS positive
edge triggered D flip-flop for CLK = 0 and for CLK = 1 are also shown in Fig. 2.16(b). When CLK = 0,
both latches will be isolated from each other and the slave latch holds the previous value, and the master
latch (negative level sensitive latch) follows the input (Qm = D′). When CLK changes from 0 to 1, the
transmission gate closest to data D will become open and the master latch forms a closed loop and holds
the value of D at the time of clock transition from 0 to 1. The slave latch feedback loop is now open,
and it is now connected to the master latch through a transmission gate. Now the open slave latch passes
the value held by the master (Qm = D′) to the output. The output Q = Q′ m,
which is the value of the input
D at the time of the clock transmission from 0 to 1. Since the master is disconnected from the data input
D, the input D cannot affect the output. When the clock signal changes from 1 to 0, the slave forms a
feedback loop, saving the value of the master and the open master start to sampling and following the
input data D again. But, as is evident from the Fig. 2.16(b), this will not affect the output. Together with
RAM and ROM, which are explained in the section on Memory Circuits, these structures form the basis
of most CMOS storage elements and are also used as the memory element in the design of sequential
circuits. Figure 2.16(c) shows the CMOS realization of the positive edge triggered D flip-flop, including
the transistors required for generating the CLK′ signal—18 transistors are required for its implementation.
© 2002 by CRC Press LLC