U. Glaeser

FIGURE 31.19 90 o locking using XOR (a) and ring-oscillator (b).
Minimizing Jitter
Jitter in the sampling clock is primarily due to the sensitivity of the loop elements to supply noise. Although
the feedback system can correct for noise with frequencies below the bandwidth of the loop, highfrequency
noise can appear as jitter on the output clocks. Loop elements, especially oscillator or delayline
buffer elements, are often differential and have high common-mode and supply rejection to minimize
the noise. Oscillators in particular are carefully designed because noise causes errors in frequency [32].
Phase error accumulates because it is the integral of the frequency error.
Many clocks drive large capacitances. Clock buffers are typically CMOS inverters for power efficiency,
but they have much higher supply sensitivity than the delay buffers 21 and cause over half of the total jitter
of the output clock. Dummy clock buffers are often included in the feedback of the PLL (Fig. 31.17) to
use the feedback loop to track out the low frequency portion of the noise [1,21]. A well-designed loop
in a system with 5% supply noise will often have a jitter roughly 0.5 of the delay of a FO-4 inverter 22 of the
clock period. Intrinsic jitter without supply noise can be more than three times less.
Phase Detection and Static Phase Offsets
In addition to the jitter, dc phase offsets are equally important in maximizing the timing margin. Using
a loop that integrates the phase error helps reduce any inherent offsets. The offset primarily depends on
any errors in the time spacing between sampling clocks when demultiplexing, and the mismatch between
the phase detector and the receiver.
In a 1:2 demultiplexing receiver, the clock (0°) and its complement (180°) are used. Duty cycle errors
can cause one receiver to not sample at its optimal location. Typically, a correction loop is added to the
PLL output to guarantee 50% duty cycle 23 [31]. The loop averages a clock waveform to determine the
duty cycle. Using the information, the duty cycle can be adjusted by changing the logical threshold of a
clock buffer.
To sample at the middle of a data bit, a clock must be 90° shifted with respect to the data. This shift can
be achieved by either (1) using a phase detector that indicates zero error when the difference is 90° [42], or
(2) locking to 0° and shifting the clock by 90°. The first method employs XORs in the design of the phase
detector. Figure 31.19(a) illustrates a simple case, when the reference input and loop output are two clock
waveforms. The XOR output has equal high and low durations when the clocks are 90° apart. In the second
method shown in Fig. 31.19(b), reference and loop output are locked in-phase. Using a ring-oscillator with
even number of stages, an internal clock phase in the ring can be tapped for the 90° clock [27,49].
A common error in phase locking is that the receiving comparator has a nonzero setup time. To
optimally sample the data, the clock position should be adjusted for the setup time. 24 An additional delay
21
A 1% change in supply yields roughly a 1% change in delay, which can be 10× that of delay buffers.
22
For a figure relatively insensitive to PVT, the time can be normalized relative to the delay of a FO-4 inverter.
23
A higher degree of demultiplexing requires multiple phases to be generated and tuning of each phase position [52].
24
An error that is not easily dealt with is any data dependent setup time variations. This can be minimized by
designing the receiver for low input-offset voltage and hysteresis.
© 2002 by CRC Press LLC
in
ref
XOR
up
down
Quadrature output from
oscillator/delay line
phase relationship of
180o Up/Down pulses are equal width
only when in and ref are clocks
90 o with phase difference of 90
data
sampling edge
edge lock
to input
o
(a) (b)