U. Glaeser

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In the message passing model, inter-thread communication occurs only through explicit I/O operations called messages. That is, the inter-thread communication is integrated at the I/O level rather than at the memory level. The messages are of two kinds—send and receive—and their variants. The combination of a send and a matching receive accomplishes a pairwise synchronization event. Several variants of the above synchronization event are possible. Message passing has long been used as a means of communication and synchronization among cooperating processes. Operating system functions such as sockets serve precisely this function. Inter-Thread Synchronization Synchronization involves coordinating the results of a set of parallel threads into some merged result. An example is waiting for one thread to finish filling a buffer before another begins using the data. Synchronization is achieved in different ways: • Control Synchronization: Control synchronization depends only on the threads’ control state and is not affected by the threads’ data state. This synchronization method requires a thread to wait until other thread(s) reach a particular control point. Examples for control synchronization operations are barriers and critical sections. With barrier synchronization, all parallel threads have a common barrier point. Each thread is allowed to proceed after the barrier only after all of the spawned threads have reached the barrier point. This type of synchronization is typically used when the results generated by the spawned threads need to be merged. With critical section type synchronization, only one thread is allowed to enter into the critical section code at a time. Thus, when a thread reaches a critical section, it will wait if another thread is currently executing the same critical section code. • Data Synchronization: Data synchronization depends on the threads’ data values. This synchronization method requires a thread to wait at a point until a shared name is updated with a particular value (by another thread). For instance, a thread executing a wait (x == 0) statement will be delayed until x becomes zero. Data synchronization operations are typically used to implement locks, monitors, and events, which, in turn, can be used to implement atomic operations and critical sections. When a thread executes a sequence of operations as an atomic operation, other threads cannot access any of the (shared) names updated during the atomic operation until the atomic operation has been completed. Coherence and Consistency The last aspect that we will consider about the parallel programming model is coherence and consistency when threads share a name space. Coherence specifies that the value obtained by a read to a shared location should be the latest value written to that location. Notice that when a read and a write are present in two parallel threads, coherence does not specify any ordering between them. It merely states that if one thread sees an updated value at a particular time, all other threads must also see the updated value from that time onward (until another update happens to the same location). The consistency model determines the time at which a written value will be made visible to other threads. It specifies constraints on the order in which operations to the shared space must appear to be performed (i.e., become visible to other threads) with respect to one another. This includes operations to the same locations or to different locations, and by the same thread or different threads. Thus, every transaction (or parallel transactions) transfers a collection of threads from one consistent state to another. Exactly what is consistent depends on the consistency model. Several consistency models have been proposed: • Sequential Consistency: This is the most intuitive consistency model. As per sequential consistency, the reads and writes to a shared address space from all threads must appear to execute serially in such a manner as to conform to the program orders in individual threads. This implies that the overall order of memory accesses must preserve the order in each thread, regardless of how instructions from different threads are interleaved. A multiprocessor system is sequentially consistent if it always produces results that are same as what could be obtained when the operations of all threads © 2002 by CRC Press LLC
are executed in some sequential order [20]. Sequential consistency is very restrictive and prevents the multiprocessor hardware from performing many optimizations to improve performance. • Weak Consistency: This consistency model [6] relaxes the constraints imposed by sequential consistency by relating memory access order to synchronization points in the program. That is, sequential consistency is maintained among the synchronization accesses. In addition, a synchronization access serves as a barrier by enforcing that all previous memory accesses must be completed before performing a synchronization access, and no subsequent memory accesses can be performed before completing a synchronization access. In addition to weak consistency, several other relaxed consistency models have been proposed—release consistency [12], processor consistency [13], etc. Partitioning a Program into Threads Thread selection involves partitioning a control flow graph (CFG) into threads. Given a particular parallel programming model (inter-thread communication model as well as thread sequencing model), how should the parallelizer go about deciding where the thread boundaries should be? Perhaps the most important issue in multiprocessing/multithreading is the basis used for partitioning a program into threads. The criterion used for partitioning is very important, because an improper partitioning could in fact result in high inter-thread communication and synchronization, thereby degrading performance! True multithreading should not only aim to distribute instructions evenly among the threads, but also aim to minimize inter-thread communication by localizing a major share of the inter-instruction communication occurring in the processor to within each PE. In order to achieve this, mutually data dependent instructions are most likely allocated to the same thread. This is somewhat hard, because programs are currently written in control-driven form, which often causes individual strands of data-dependent instructions to be spread over a large segment of code. Thus, the partitioning software has to first construct the data flow graph (DFG), and then do the program partitioning. Notice that if programs were specified in data-driven form as in the dataflow computation model [17], taking data dependences into account would have been simpler. Thread selection is a difficult problem, because we need to consider many issues such as PE utilization, load balancing, control independence of threads (thread prediction accuracy for SpMT models), and inter-thread data dependences. Often, trying to make optimizations for one area will have a negative effect on another. Who Does the Program Partitioning? Program partitioning can be done by the programmer, compiler, or run-time hardware. Depending on who does the partitioning, the type of analysis that can be done will be different. • Programmer: In this approach, the programmer explicitly represents the threads in the high-level language program. In order to do this, three types of extensions are provided at the high-level language level: (i) multithreading library, (ii) language extensions, and (iii) compiler directives. Examples for this approach are EARTH [21] and XMT [37]. All of these use the parallel threads model. Notice that the compiler has to be modified to handle these extensions. The compiler does not, however, make decisions on where to do the partitioning. It is interesting to note that although conventional multiprocessors have been commercially available for quite some time, only a small fraction of the software has been written so far to exploit parallelism. • Compiler: In this case, the compiler takes a sequential program and partitions it into threads. The main advantage of deferring program partitioning to the compiler is that it frees the programmer from reasoning about parallel threads. Its main advantages with respect to hardware-based partitioning are that it does not add to the complexity of the processor, and that it has the ability to perform complex pre-partitioning and post-partitioning optimizations that are difficult to perform at run-time. Compiler-directed partitioning algorithms are generally insensitive to the number of PEs in the processor, however, its partitioning decisions need to be conveyed to the © 2002 by CRC Press LLC
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© 2002 by CRC Press LLC
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© 2002 by CRC Press LLC Fernanda p
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Locating Your Topic Several avenues
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Krste Asanovic Massachusetts Instit
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7 8 9 Architectures for Low Power P
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SECTION VII Communications and Netw
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45 Testing of Synchronous Sequentia
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Hiroshi Iwai Tokyo Institute of Tec
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FIGURE 1.2 FIGURE 1.3 © 2002 by CR
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1.2 Downsizing below 0.1 © 2002 by
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FIGURE 1.9 Subthreshold leakage cur
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FIGURE 1.13 Epitaxial channel [9].
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gate length reduction was accelerat
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of the prediction. Until only sever
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FIGURE 1.22 Clarke number of elemen
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1.5 Source and Drain Figure 1.25 sh
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FIGURE 1.27 Retrograde profile. FIG
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TABLE 1.6 Trend of Interconnect by
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TABLE 1.9a Trend of DRAM Cell: Stac
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FIGURE 1.36 Trend of gate length. F
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References 1. D. Kahng and M. M. At
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40. B. H. Lee, R. Choi, L. Kang, S.
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outputs of the gate regardless of t
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FIGURE 2.4 circuit. This is the bas
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FIGURE 2.8 Two different realizatio
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FIGURE 2.12 Multifunction circuitry
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Dynamic Logic Circuits The basic id
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transistors in the pull-down networ
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In Fig. 2.21(d), the cross-coupled
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FIGURE 2.23 Different configuration
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In some literature, the authors lik
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Concluding Remarks The feature size
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FIGURE 2.30 Other pass-transistor c
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FIGURE 2.34 Dual-rail, pass-transis
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Shannon expansion, as shown below,
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FIGURE 2.41 Logic circuit for Out =
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FIGURE 2.45 Example decomposed BDD.
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FIGURE 2.50 Diffusion-area sharing
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FIGURE 2.54 Relationship between co
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29. Shiple, T. R., Hojati, R., Sang
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FIGURE 2.58 DTMOS devices: (a) stan
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the design into a BDD representatio
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FIGURE 2.63 Circuit diagram of 2-in
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FIGURE 2.67 Synthesis of 2-input AN
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pass-transistor logic, constrained
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16. Bryant, R., Graph-based algorit
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As shown in Fig. 2.79, the MOSFET d
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n + SiO 2 FIGURE 2.80 No reverse bo
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structures are a powerful solution
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SiO 2 Epitaxial Si Double Layered P
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PD-SOI Application to High-Performa
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LO FIGURE 2.91 History effects. sta
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weight, lower cost, a wireless inte
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TABLE 2.7 Performance of sub-1 V MT
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X X FIGURE 2.99 1 V A/D converter u
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When the communication range is 10
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13. Nakashima, S., et al., Thicknes
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FIGURE 3.1 Conventional ECL circuit
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FIGURE 3.4 FIGURE 3.5 IPULL-DOWN, f
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FIGURE 3.7 V REG voltage regulator
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FIGURE 3.10 Layout of inverter gate
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FIGURE 3.14 Power consumption versu
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I/O Pads, is 60 mW for the multiple
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FIGURE 3.21 Maximum data rate vs. V
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John C. McCallum National Universit
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enchmark took between 15.7 and 5115
Page 140 and 141: The improvements in line widths, ch
Page 142 and 143: performance. Extensive lists of SPE
Page 144 and 145: TABLE 4.6 Functions of Memory and S
Page 146 and 147: Memory Price ($/MB) FIGURE 4.3 Cost
Page 148 and 149: TABLE 4.8 Disk Drive Characteristic
Page 150 and 151: 4.6 Summary The performance of comp
Page 152 and 153: 53. Curnow, H. J., and Wichmann, B.
Page 154 and 155: Computer Systems and Architecture
Page 156 and 157: advances that have been made in dev
Page 158 and 159: Server Types Servers are optimized
Page 160 and 161: Total Cost of Ownership Another con
Page 162 and 163: edundant memory-bit steering, and s
Page 164 and 165: majority of the users. Hardware opt
Page 166 and 167: processor implementations. In later
Page 168 and 169: FIGURE 5.7 an operand. For larger c
Page 170 and 171: Example 2 This example contrasts th
Page 172 and 173: Unlike the Defoe, the IA-64 archite
Page 174 and 175: This 3-phase approach fails to expl
Page 176 and 177: 6. Scott Rixner, William J. Dally,
Page 178 and 179: Shared-memory vector architectures
Page 180 and 181: The vector ISA usually fixes the ma
Page 182 and 183: FIGURE 5.12 A vector unit construct
Page 184 and 185: use of loops optimized for certain
Page 186 and 187: 9. Espasa, R., Advanced Vector Arch
Page 188 and 189: thread management (including run-ti
Page 192 and 193: multithreaded hardware, possibly by
Page 194 and 195: synchronization) and usually contai
Page 196 and 197: a common register space, it is impo
Page 198 and 199: FIGURE 5.16 When a load request is
Page 200 and 201: list a few helpful references to wh
Page 202 and 203: 38. S. Wallace, B. Calder, and D. T
Page 204 and 205: Of course, SIMD machines have limit
Page 206 and 207: computation, it will decrease execu
Page 208 and 209: FIGURE 5.19 An 8 × 8 baseline netw
Page 210 and 211: Since then, we have seen constant e
Page 212 and 213: Stack: Data: Text: Virtual Space FI
Page 214 and 215: FIGURE 5.25 Shared memory. Shared m
Page 216 and 217: 0 2 GB Text Init. Data Bss Heap . .
Page 218 and 219: In general, if the necessary transl
Page 220 and 221: Mark Smotherman Clemson University
Page 222 and 223: Studies of Instruction-Level Parall
Page 224 and 225: Modern Designs Most high-performanc
Page 226 and 227: The principle of register renaming
Page 228 and 229: FIGURE 6.2 issued into the RS, (ii)
Page 230 and 231: Issue Dispatch FIGURE 6.4 The proce
Page 232 and 233: FIGURE 6.6 Scope of register renami
Page 234 and 235: FIGURE 6.9 State transition diagram
Page 236 and 237: Thus, the maximal number of instruc
Page 238 and 239: In addition, if rename buffers are
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it, whose role will be explained su
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As Fig. 6.13 shows, the latest proc
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for recovery. Both processors incor
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FIGURE C. The principle of direct i
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13. White, S. and Reysa, J., PowerP
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FIGURE 6.14 A branch flowing throug
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is that mispredictions limit the pr
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fetch engine to identify which inst
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FIGURE 6.17 A schematic for a bimod
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FIGURE 6.20 A schematic for a GAg g
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FIGURE 6.22 A schematic for a hybri
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time this branch is seen, those bit
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FIGURE 6.23 Branch prediction accur
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11. Price, C., MIPS IV Instruction
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transporting digital bits, whereas
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FIGURE 6.25 The system architecture
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Finally, because the main task of n
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Pradip Bose IBM T. J. Watson Resear
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frequency © 2002 by CRC Press LLC
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The “mips” metric for performan
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Hence, in this paper, we do not dwe
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FIGURE 7.4 Parallel SIMD architectu
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dynamic prediction of such idle mod
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FIGURE 7.7 High-level block-diagram
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(measured as a performance over pow
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Steady-state BIPS FIGURE 7.9 Perfor
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8. Larson, A. G., “Cost-effective
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Jozo J. Dujmović San Francisco Sta
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x FIGURE 8.1 Movement of the disk I
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The critical distance x ∗ is Ther
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Hence, the average seek time for th
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FIGURE 8.4 Four-parameter exponenti
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Access Time [ms] 2 0 0 FIGURE 8.6 M
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TABLE 8.1 Classification of Eight B
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The traditional load independent me
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Response Time [seconds] 290 270 250
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FIGURE 8.14 Prediction errors e(p)
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8.2 Performance Evaluation: Techniq
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is generally the most important mea
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tool to profile programs on the Alp
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driven simulation has two major pro
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A variety of profiling tools exist
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SPLASH, the SPLASH suite was create
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different types and complexity eith
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Table 8.8 provides sources for the
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37. MediaBench benchmarks, http://w
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(a) Instruction Cache (b) Trace Cac
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PE 0 Local Register File local bypa
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The large trace processor instructi
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11. S. Melvin, M. Shebanow, and Y.
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complement numbers. Sign magnitude
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where ak, bk, and ck are the inputs
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k + 1, etc. Extending to a third st
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a 12:15 b 12:15 4-Bit RCA s 12:15 F
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FIGURE 9.8 Two’s complement subtr
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FIGURE 9.10 Unsigned 6 by 6 array m
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Digit Recurrent Division The most c
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FIGURE 9.14 Nonrestoring division.
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The Newton-Raphson division algorit
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FIGURE 9.18 Floating-point addition
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9.2 Fast Adders and Multipliers Gen
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FIGURE 9.20 Half-adder circuit. is
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gi pi FIGURE 9.22(b) Carry skip cir
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Assuming that a single level of the
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Array-Type Multiplier The simplest
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p1i,j p2i,j p3i,j p4i,j FIGURE 9.27
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The partial product PP j is to be c
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The sum SGN of the whole extended b
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FIGURE 9.31 54 × 54-bit parallel m
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6. Svensson, C. and Tjarnstrom, R.,
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Design Techniques III 10 Timing and
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FIGURE 10.1 Typical chip interface.
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Loop Components PLLs and DLLs share
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delay is some fraction of the input
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esults from the voltage across the
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© 2002 by CRC Press LLC TABLE 10.2
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db(H( ω)) FIGURE 10.6 PLL closed-l
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ω )/G O) db(T(ω ph(T( )/π) FIGUR
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Phase Margin (deg) FIGURE 10.10 PLL
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FIGURE 10.11 Measured PLL jitter hi
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FIGURE 10.13 DLL output jitter sens
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FIGURE 10.18 PLL output jitter sens
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Active supply filters employ amplif
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FIGURE 10.19 Single-ended delay ele
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Frequency (GHz) FIGURE 10.23 Freque
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FIGURE 10.25 Push-pull charge pump.
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Circuit Summary In general, all DLL
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5. T. Lee, et al., “A 2.5V CMOS D
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introduced in [3], is used to repre
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FIGURE 10.31 Setup and hold time ti
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FIGURE 10.34 Max-timing diagrams fo
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FIGURE 10.37 Time borrowing for sin
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FIGURE 10.39 Max-timing for single-
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Min-Timing In contrast to max-timin
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FIGURE 10.46 Min-timing diagrams fo
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FIGURE 10.49 Edge-triggered, flip-f
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FIGURE 10.51 FIGURE 10.52 Max-timin
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FIGURE 10.53 Transparent-high latch
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FIGURE 10.57 Complementary TSPC tra
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FIGURE 10.61 A positive, edge-trigg
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FIGURE 10.66 Pulsed latches. FIGURE
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assigned, based on the subcircuit t
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FIGURE 10.71 Scan chain for dual-ph
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and SEB, which are complementary, c
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when used as a flip-flop, the NAND3
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FIGURE 10.75 Integrated memory for
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Memory Cell Bit# Bit FIGURE 10.78 A
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FIGURE 10.80 Modeling process varia
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FIGURE 10.83 A column circuit. FIGU
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advantage of this circuit, compared
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K. Wayne Current University of Cali
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11.2 Nonvolatile Multiple-Valued Me
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Multiple-Valued EEPROM and Flash Me
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direct properly scaled and logicall
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Current comparators are a critical
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FIGURE 11.4 Current-mode CMOS quate
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FIGURE 11.6 Current-mode CMOS quate
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observed with these circuits are ab
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FIGURE 11.11 Current-mode CMOS quat
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FIGURE 11.12 Current-mode CMOS latc
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FIGURE 11.14 Current-mode CMOS anal
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esults confirm the DC transfer func
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19. T. T. Dao, “Threshold I2L and
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FIGURE 12.1 Device technologies use
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selected depending on the number of
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Architecture of Newer Generation FP
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FIGURE 12.6 An example of a simple
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tools, the + 1 operation is a speci
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download the programming data to th
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FIGURE 13.1 High-performance microp
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FIGURE 13.4 TABLE 13.1 combinationa
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accurate wire modelling while limit
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FIGURE 13.6 Dual-rail, multiple-out
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FIGURE 13.10 Effect of output inver
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FIGURE 13.11 Unfooted dynamic 4:1 m
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(4) the limit of designers to manag
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© 2002 by CRC Press LLC IV Design
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FIGURE 14.1 FIGURE 14.2 newer semic
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The cost impact of power consumptio
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In any case, the move toward “Gre
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This static current is obviously un
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14.2 Power Estimation As we saw in
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lock as a function of various param
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FIGURE 14.8 Sleep transistors to co
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FIGURE 14.12 Data enabling. In addi
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Power Reduction through CAD Tools P
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AMPS AMPS is a circuit power optimi
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Masayuki Miyazaki Hitachi, Ltd. 15.
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15.3 Supply Voltage Management Supp
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FIGURE 15.4 MT-CMOS balloon circuit
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FIGURE 15.9 EVT-CMOS circuit design
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FIGURE 15.12 VT-CMOS block diagram
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FIGURE 15.15 SA-V t CMOS scheme wit
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FIGURE 15.17 Floating-point datapat
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Vivek De Intel Corporation Ali Kesh
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FIGURE 16.3 n-channel ID vs. VG sho
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Gate-Induced Drain Leakage (I 4) GI
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FIGURE 16.7 Two-nMOS stack in a two
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FIGURE 16.11 Four-input NAND NMOS s
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FIGURE 16.12 Distribution of standb
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Die count FIGURE 16.16 (a) Adaptive
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due to adaptive body bias worsens w
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Thomas D. Burd University of Califo
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the parameter to be maximized since
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17.3 Dynamically Varying Voltage If
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The voltage converter required for
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FIGURE 17.7 DVS improvement for UI
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FIGURE 17.10 Measured throughput vs
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FIGURE 17.12 Sources of noise margi
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FIGURE 17.15 Ring oscillator adapti
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FIGURE 17.17 Sense-amp delay variat
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Christian Piguet CSEM: Centre Suiss
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Some Basic Rules There are some bas
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TABLE 18.2 Looped 8-bit Multiply Pr
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FIGURE 18.4 new architecture paradi
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FIGURE 18.6 FIGURE 18.7 the second
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FIGURE 18.9 FIGURE 18.10 With latch
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18.6 Low-Power Memories As memories
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connected to the main bitline (only
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is today only about a factor of 2 d
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Katsunori Seno SONY Corporation 19.
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FIGURE 19.2 FIGURE 19.3 This is a c
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FIGURE 19.6 FIGURE 19.7 FPGA sacrif
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FIGURE 19.9 RAWn precharge FIGURE 1
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a fixed given standard. References
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Hendrawan Soeleman Purdue Universit
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for a short period of time when bot
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Total Average Power Putting togethe
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Signal Probability Calculation In c
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Example Given y = x 1 + x 2. Find P
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A B F FIGURE 20.7 Unfactorized and
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etween successive transitions is a
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FIGURE 20.9 A logic gate and its co
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Results Using Probabilistic Techniq
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FIGURE 20.12 Probabilistic and stat
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14. VLSI Microprocessors: A Guide t
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0 V to a voltage V in time T throug
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a small fraction of circuit nodes t
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FIGURE 21.6 (a) E-R latch, (b) timi
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FIGURE 21.8 Potential E-R latch for
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The only difference between the two
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FIGURE 21.14 (a) Clock-powered stat
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FIGURE 21.17 The three drivers used
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FIGURE 21.20 Energy-delay product (
Page 648 and 649:
FIGURE 21.22 AC-1 clock-driver sche
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clock-powered nodes accounted for 8
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Two generations of clock-powered mi
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29. Athas, W. C., Tzartzanis, N., M
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Wayne Wolf Princeton University 22.
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so a CPU could be built in reconfig
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optimized processes. Although embed
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FIGURE 22.4 they are most useful wh
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• How should processes be allocat
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25 memory system activity. If the c
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Jonathan W. Valvano University of T
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FIGURE 23.2 6808, I/O ports A and B
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personnel so that they are proficie
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BDM can provide the ability to obse
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minor modifications to the finite s
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Many components are included in a d
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will saturate resulting in a bang-b
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Two approaches are used to synchron
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Fred J. Taylor University of Florid
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The output of a linear system havin
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FIGURE 24.2 Effects of windowing an
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frequency range ±f Nyquist = ±f s
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performance, complexity, and precis
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overflows of intermediate sums. Tha
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24.7 Applications “DSP” has bec
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DSP (Digital Signal Processor) or D
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PC as a Terminal (Modem) The PC is
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characteristics: • Fixed pictures
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HDTV (and Digital Television) If th
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Modem Banks This is the first of th
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25.7 Automotive, Industrial Althoug
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36. MITEL Semiconductor: www.semico
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26.2 Digital Filters The theory of
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|H | 1 FIGURE 26.1 Frequency select
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TABLE 26.1 Filter Design Comparison
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frequency response involves some al
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Impulse Response 0.2 0.15 0.1 0.05
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This constrained magnitude problem
Page 724 and 725:
FIGURE 26.8 Block diagram of the ge
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11. Ikehara, M., Tanaka, H., and Ku
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Adam Dabrowski Poznan University To
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−12 2 The reference in this case
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FIGURE 27.1 Two-band filter bank: (
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FIGURE 27.5 Critical bandwidth and
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FIGURE 27.7 Threshold of audibility
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FIGURE 27.10 Critical band index in
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FIGURE 27.13 Simplified model of th
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All described masking effects are e
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where From Eqs. (27.32) and (27.33)
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eal-time. Although floating-point p
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FIGURE 27.19 Overlapped, power comp
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FIGURE 27.21 Symmetrical FIR filter
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In the MPEG-1 encoder an efficient
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These first two approaches can be m
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FIGURE 27.27 ADPCM: (a) encoder, (b
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FIGURE 27.30 General scheme of the
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A new standard MPEG-7, named the mu
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FIGURE 27.32 AC-3 encoder. FIGURE 2
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29. Marven, C. and Ewers, G., A sim
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FIGURE 28.1 FIGURE 28.2 of the huma
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FIGURE 28.5 image of reasonable qua
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Consider the case of a simple 2-D
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FIGURE 28.8 A sampled spatiotempora
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oth high spatial frequency componen
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If it were separable (that is, H(ξ
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The first hypothesis (the less plau
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FIGURE 28.17 The real (top) and ima
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FIGURE 28.18 The resolution of a ti
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FIGURE 28.20 Motion estimation by b
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where the superscripts n and n + 1
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must be found via a finite set of o
Page 790 and 791:
The methods in this subsection are
Page 792 and 793:
FIGURE 28.28 The split phase. Using
Page 794 and 795:
35. Y.-T. Wu, T. Kanade, J. Cohn, a
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29.2 Power Dissipation in Digital C
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additional power benefits. Efficien
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Power savings are higher than simpl
Page 802 and 803:
A priori knowledge of data stream d
Page 804 and 805:
FIGURE 29.7 DCT Chip [my DCT] avera
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19. S. Uramoto et al. A 100 MHz 2-D
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Anna Hać University of Hawaii 30.1
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Using TCP/IP also makes the network
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this is for one mobile host which i
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TDMA Time-division multiple access
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path delay. The two measures of the
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are under the control of the system
Page 820 and 821:
the bandwidth reserved in the targe
Page 822 and 823:
Chik-Kong Ken Yang University of Ca
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FIGURE 31.3 attenuation (dB) -3.0 -
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FIGURE 31.5 to handle large voltage
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p_o V bias FIGURE 31.8 High-impedan
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out[n] a0 FIGURE 31.11 Transmitter
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FIGURE 31.15 Receiver design using
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digitally by first feeding the inpu
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FIGURE 31.19 90 o locking using XOR
Page 838 and 839:
Power of these links is becoming an
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46. Takahashi, T. et al., “A CMOS
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Many computer programs exhibit some
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32.3 Related Memory Models, Hierarc
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32.6 External Sorting and Related P
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uns, each striped across the disks.
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Matrix transposition is the special
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of satellite images is over one ter
Page 854 and 855:
TABLE 32.3 Best Known I/O Bounds fo
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e accessed directly in a single I/O
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implementations of priority queues
Page 860 and 861:
By the reduction in [52], a data st
Page 862 and 863:
set of experiments on various text
Page 864 and 865:
3. A. Acharya, M. Uysal, and J. Sal
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44. J. L. Bentley and J. B. Saxe. D
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85. P. Ferragina and F. Luccio. Dyn
Page 870 and 871:
128. V. Kumar and E. Schwabe. Impro
Page 872 and 873:
173. H. Samet. The Design and Analy
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Peter J. Varman Rice University 33.
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need for fast transfers, up to 1 Gb
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In contrast to prefetching that mas
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The ERF algorithm was analyzed in [
Page 882 and 883:
increment lowestPriorityOnDisk(disk
Page 884 and 885:
External or out-of-core algorithms
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33. M. Kallahalla and P. J. Varman.
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advanced, reaching the point where
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FIGURE 34.3 FIGURE 34.4 defines the
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FIGURE 34.5 Trellis representation
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FIGURE 34.7 Data and servo sectors.
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References 1. S. H. Charrap, P. L.
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High-frequency noise is then remove
Page 900 and 901:
The various components of (34.3) ar
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sequences are more complex, and occ
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ange of 10 −12 -10 −15 . Anothe
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strategies are reviewed, which have
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FIGURE 34.13 Magnitude response for
Page 910 and 911:
taps as an approximation of the Typ
Page 912 and 913:
FIGURE 34.18 CTF BER performance de
Page 914 and 915:
TABLE 34.1 Examples of Equalizers I
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(i) Symbol rate VCO based timing re
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Symbol Rate Timing Recovery Schemes
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where B = B 1 + B 2 + 1 is the size
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in � out � d(k) FIGURE 34.26 Ti
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�(k) z -L FIGURE 34.27 Linearized
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10 −4 and 10 −2 . The steady-st
Page 928 and 929:
16. J. Sonntag, et al., “A high s
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y a special sequence known as the a
Page 932 and 933:
FIGURE 34.36 An example of two Gray
Page 934 and 935:
track n track n +1 FIGURE 34.38 The
Page 936 and 937:
FIGURE 34.40 The phase format. Posi
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increase linear density while mitig
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FIGURE 34.43 Two equivalent constra
Page 942 and 943:
FIGURE 34.44 Possible pairs of sequ
Page 944 and 945:
Distance δ min,C can be bounded as
Page 946 and 947:
FIGURE 34.45 Standard concatenation
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30. E. Soljanin, “On-track and of
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The next block is PRE. What is PR?
Page 952 and 953:
In the above example, we see that s
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FIGURE 34.52 Feedback detector. Cat
Page 956 and 957:
FIGURE 34.54 Decision feedback equa
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esponse (this is also valid for dif
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its use, while the computational, o
Page 962 and 963:
FIGURE 34.58 Viterbi algorithm dete
Page 964 and 965:
Noise-Predictive Maximum Likelihood
Page 966 and 967:
The error event likelihoods are cal
Page 968 and 969:
Metric-First Algorithms Metric-firs
Page 970 and 971:
termination at the same time. Howev
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13. J. Hagenauer, “Applications o
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Given a code C of length n and dime
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Notice that, although a code may ha
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Not many perfect codes exist. In th
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Theorem 1 (Shannon) For any � > 0
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If we write the codewords as polyno
Page 984 and 985:
Let © 2002 by CRC Press LLC 1 1 K
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which, in polynomial form, is Let E
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m Σl=0 because a l = (a m+1 − 1)
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Evaluating the syndromes, we obtain
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FIGURE 34.63 Interleaving m times o
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Operating System © 2002 by CRC Pre
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systems, the most notable example b
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35.3 Components of Distributed Oper
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Message-passing IPC shares many cha
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process at any arbitrary stage in i
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Few attempts were made in the past
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alternate years with SOSP), and the
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© 2002 by CRC Press LLC 42 Mobile
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FIGURE 36.1 were introduced; howeve
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FPGAs by providing on-chip memory f
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FIGURE 36.3 There is a considerable
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FIGURE 36.4 The general form of the
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FIGURE 36.6 If a VPB can cover all
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John Morris University of Western A
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FIGURE 37.1 Simplified block diagra
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inverters, and the programmable mul
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Programmable Active Memories (PAM)
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measured in megabits, not megabytes
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from modern FPGAs, e.g., Altera’s
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Regularity A processing pipeline wi
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Other Languages Other routes from h
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29. Bergmann, N.W., and Dawood, A.,
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FIGURE 37.8 Basic architectures for
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Selected Applications Several class
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Development Systems Developing appl
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implementation. Reconfigurable or r
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The designer starts the generation
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lock but allows multiple instructio
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data-types that are mapped to TIE r
Page 1052 and 1053:
Conclusions Configurable and extens
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FIGURE 38.1 Average vehicle speed.
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AHS means advanced cruise-assist hi
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TABLE 38.3 navigation systems VICS
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FIGURE 38.9 FIGURE 38.10 a map data
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FIGURE 38.13 The four basic functio
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Support of Safe Driving System The
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System evaluation, the fourth issue
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FIGURE 38.18 Summarizing the three
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uilder tools serving to build MMI o
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FIGURE 38.23 FIGURE 38.24 automaker
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FIGURE 38.26 FIGURE 38.27 The first
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FIGURE 38.30 FIGURE 38.31 a kind of
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To Probe Further In this field, the
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FIGURE 39.1 of more versatile media
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1 • 3DNow! 1 [11,12] from AMD,
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FIGURE 39.6 In the packed add instr
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If saturation arithmetic is used in
Page 1088 and 1089:
TABLE 39.1 Examples of Operations T
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FIGURE 39.10 PAVG R c, R a, R b: Pa
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FIGURE 39.13 Packed compare instruc
Page 1094 and 1095:
FIGURE 39.17 Packed multiply high i
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FIGURE 39.20 Packed multiply left i
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FIGURE 39.23 In the packed multiply
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TABLE 39.4 Packed Integer Multiplic
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Subword Permutation Instructions In
Page 1104 and 1105:
is n log 2(n). Table 39.6 shows how
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FIGURE 39.33 Mix left instruction.
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TABLE 39.7 Subword Permutation Inst
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TABLE 39.9 IA-64 uses FPMA and FPMS
Page 1112 and 1113:
The two-bit result field is written
Page 1114 and 1115:
source register. These three FP mix
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13. Motorola, “AltiVec technology
Page 1118 and 1119:
FIGURE 39.48 ManArray 1 × 2 core e
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FIGURE 39.50 Hypercube interconnect
Page 1122 and 1123:
FIGURE 39.53 Host DSP software laye
Page 1124 and 1125:
Benchmark Data Type Performance 256
Page 1126 and 1127:
FIGURE 39.56 Simplified schematic o
Page 1128 and 1129:
Gaming applications often require a
Page 1130 and 1131:
system, and the application program
Page 1132 and 1133:
FIGURE 39.60 FIGURE 39.61 FIGURE 39
Page 1134 and 1135:
FIGURE 39.64 shifting place limits
Page 1136 and 1137:
FIGURE 39.66 pitch Address Looping
Page 1138 and 1139:
FIGURE 39.69 gain of the filter. It
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as a core to integrate onto the sam
Page 1142 and 1143:
7. Rossum, D., Constraint based aud
Page 1144 and 1145:
FIGURE 39.74 Procedure for simulate
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The fitness value of an individual
Page 1148 and 1149:
FIGURE 39.77 The tabu list can be v
Page 1150 and 1151:
Intermediate-term memory component
Page 1152 and 1153:
FIGURE 39.81 Selection. FIGURE 39.8
Page 1154 and 1155:
Work on parallelization of the tabu
Page 1156 and 1157:
Acknowledgment The authors acknowle
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47. L. K. Grover. A new Simulated A
Page 1160 and 1161:
93. E. M. Rudnick, J. H. Patel, G.
Page 1162 and 1163:
138. Youn-Long Lin, Yu-Chin Hsu, an
Page 1164 and 1165:
This architecture allowed for large
Page 1166 and 1167:
FIGURE 40.3 40.3 Application Server
Page 1168 and 1169:
FIGURE 40.5 applications. CORBA cur
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FIGURE 40.8 The application server
Page 1172 and 1173:
FIGURE 40.10 The proposed architect
Page 1174 and 1175:
cost at the front end. The ideal ap
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FIGURE 40.12 Client-server and netw
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Yoshiaki Hagiwara Sony Corporation
Page 1180 and 1181:
FIGURE 41.2 This corresponds to the
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FIGURE 41.5 Buried channel CCD stru
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FIGURE 41.8 Applications of CCD and
Page 1186 and 1187:
sensor (1100 K pixel) Microphone ×
Page 1188 and 1189:
�� FIGURE 41.14 Form com
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FIGURE 41.16 Stack technology. Link
Page 1192 and 1193:
1st EmDRAM Product FIGURE 41.19 Emb
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FIGURE 41.23 Em-DRAM process techno
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John F. Alexander University of Nor
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Several reasons exist for mentionin
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sort of local area network. Support
Page 1202 and 1203:
Technological hurdles must be overc
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FIGURE 42.1 Block diagram of (a) ge
Page 1206 and 1207:
FIGURE 42.3 Alternative FIR filter
Page 1208 and 1209:
FIGURE 42.5 Polyphase filter struct
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3. E. Dahlman, Bjorn Gudmundson, M.
Page 1212 and 1213:
TABLE 42.1 Categorizing Reusable Co
Page 1214 and 1215:
FIGURE 42.11 Internet growth. FIGUR
Page 1216 and 1217:
FIGURE 42.13 Software for VoIP SoC.
Page 1218 and 1219:
FIGURE 42.17 Bandwidth trends. FIGU
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The interconnections between the va
Page 1222 and 1223:
FIGURE 42.21 A typical communicatio
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carry information over longer dista
Page 1226 and 1227:
however, it is not uncommon that so
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node, to which the user is connecte
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its information. Intuitively, this
Page 1232 and 1233:
This issue is referred to as latenc
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Evolution of Standard Image/Video C
Page 1236 and 1237:
FIGURE 42.26 Sequence of zigzag-cod
Page 1238 and 1239:
FIGURE 42.29 150th Frame of origina
Page 1240 and 1241:
FIGURE 42.31 Data partitioning for
Page 1242 and 1243:
for transmitting a predictively cod
Page 1244 and 1245:
42.6 Pen-Based User Interfaces—An
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FIGURE 42.35 The handwriting recogn
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• No toggling between edit/contro
Page 1250 and 1251:
FIGURE 42.39 Boxplots of time to en
Page 1252 and 1253:
0 … 9 ( ) -
Page 1254 and 1255:
is using the SMIL generic media ref
Page 1256 and 1257:
FIGURE 42.47 Example of pen-and-pap
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slots specifying pieces of informat
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most stringent demands for low-powe
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FIGURE 42.51 MIPS requirement of se
Page 1264 and 1265:
FIGURE 42.54 von Neumann architectu
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FIGURE 42.57 Dual Mac architecture
Page 1268 and 1269:
FIGURE 42.59 Two data path variatio
Page 1270 and 1271:
FIGURE 42.60 Basic pipeline archite
Page 1272 and 1273:
References 1. Bahl L., Cocke J., Je
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Random Oracle Model One direction o
Page 1276 and 1277:
at the end of its usefulness. A new
Page 1278 and 1279:
function and verification function
Page 1280 and 1281:
underlies the Diffie-Hellman key ag
Page 1282 and 1283:
31. Dolev, D., Dwork, C., and Naor,
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R. Chandramouli Synopsys Inc. 44.1
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many deficiencies in the design may
Page 1288 and 1289:
impact the performance and test ove
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FIGURE 44.4 FIGURE 44.5 It becomes
Page 1292 and 1293:
SoC methodologies require synchroni
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This method, however, lacks the app
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FIGURE 45.2 Input formats of MILEF
Page 1298 and 1299:
FIGURE 45.3 FIGURE 45.4 Robustness
Page 1300 and 1301:
FIGURE 45.5 In Fig. 45.5 a simple e
Page 1302 and 1303:
difficult to identify for overcurre
Page 1304 and 1305:
General Approach in Comparison with
Page 1306 and 1307:
FIGURE 45.10 phase—the propagatio
Page 1308 and 1309:
shorter test sequence could possibl
Page 1310 and 1311:
Looking at results of Table 45.6, i
Page 1312 and 1313:
45.4 Summary Automatic test pattern
Page 1314 and 1315:
41. F. Brglez, H. Fujiwara: A neutr
Page 1316 and 1317:
FIGURE 46.1 Rule of ten in testing
Page 1318 and 1319:
FIGURE 46.5 FIGURE 46.6 of the DUT.
Page 1320 and 1321:
FIGURE 46.7 generate tests for ever
Page 1322 and 1323:
FIGURE 46.9 FIGURE 46.10 behavioral
Page 1324 and 1325:
Z. Stamenković University of N. St
Page 1326 and 1327:
FIGURE 47.2 Murphy’s Model The mo
Page 1328 and 1329:
where k is the total number of crit
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FIGURE 47.5 Definition of IC critic
Page 1332 and 1333:
distribution [34,35]: © 2002 by CR
Page 1334 and 1335:
and, in the case of w = X 2 − X 1
Page 1336 and 1337:
Algorithm • Input: a singly linke
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TRACIF takes a CIF file as input an
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TABLE 47.2 Critical Area Extraction
Page 1342 and 1343:
Also, the critical areas for lithog
Page 1344 and 1345:
(enhancement of the process cleanli
Page 1346 and 1347:
28. Corsi, F. and Martino, S., Defe
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U. Glaeser

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