U. Glaeser

FIGURE 42.3 Alternative FIR filter structures: (a) Direct form FIR structure, (b) Transposed form FIR structure,
and (c) Hybrid FIR structure.
VLSI Architectures for Signal Processing Blocks
Fixed Coefficient Filters
The most intuitive means of implementing a FIR filter is to use the direct form implementation presented in
Fig. 42.3(a) [12]. Applying the transposition theorem to this filter we get the transposed structure shown in
Fig. 42.3(b). The two structures are identical in terms of I/O, however, the transposed form is ideal for high
speed filtering operations since the critical path for an N tap filter is always one multiplier delay plus one
adder delay. The critical path of the direct form, however, is one multiplier delay plus N-1
adder delays. The
fact is that the symbol rate for most wireless communication systems is a few tens of megahertz, whereas a
typical multiplier in today’s CMOS process technologies can easily reach speeds of 80–100 MHz. It is thus
desirable to use the hybrid architecture shown in Fig. 42.3(c) where each multiplier accumulator is timeshared
between several taps (three in this case) resulting in a more compact circuit for lower symbol rates.
The implementation of fixed coefficient FIR filters can be further simplified by moving away from the
use of 2’s complement number notation, and using a signed-digit number system in which each digit
can take on one of three values { −1,
0, 1}. In general there are multiple signed-digit representations for
the same number and a canonic signed-digit (CSD) representation can be defined for which no two
nonzero digits are adjacent [8]. The added flexibility of signed-digit numbers allows us to realize the
same coefficient using fewer nonzero coefficients than would be possible with a simple 2’s complement
representation. Using an optimization program, it is possible to design an FIR filter using CSD filters
with as few as three or four nonzero digits for each coefficient. This could help significantly reduce the
complexity of fixed coefficient multipliers since the number of partial products generated is directly
proportional to the number of nonzero digits in the multiplier.
Direct Digital Frequency Synthesizer (DDFS)
Given an input frequency word W,
a DDFS will produce a frequency proportional to W.
The most common
techniques for realizing a DDFS consist of first accumulating the frequency word W in a phase accumulator
and then producing the sine and cosine of the phase accumulator value using a table lookup or a
© 2002 by CRC Press LLC
(a)
(b)
(c)
z -1
W 0 W 1 W 2 W N-1
W N-1 W N-2 W 1 W 0
z -1
W 5 W 4 W 3
z -1
z -1
W 2 W 1 W 0
z -1
z -1