U. Glaeser

0 V to a voltage V in time T through a resistance R from a voltage-ramp source, the energy dissipated
in the resistance, , is [4,5]:
© 2002 by CRC Press LLC
E
vrs
E vrs
RC
------ ⎛RC ------ ⎞
T ⎝ T ⎠
2
RC
– ⎛------ ⎞
⎝ T ⎠
2 – ------
⎛ RC
+ e ⎞ 2
=
CV
⎝ ⎠
For T → 0, the voltage-ramp source becomes equivalent to a dc source. Indeed, for
reduces to:
E dcs
1
-- CV
2
2
which denotes the energy required to charge a capacitance
Eq. (21.1) can be approximated by [6,7]:
E ccs
=
⎛RC ------ ⎞ 2
= CV
⎝ T ⎠
(21.1)
T → 0 Eq. (21.1)
(21.2)
C from a dc source of voltage V.
For T >> RC,
(21.3)
Equation (21.3) gives the energy dissipated in the resistance R if a constant-current source is used to
charge the capacitance C to voltage V in time T.
It can be proved [8] that constant-current charging
results in minimum energy dissipation for a given charging time T.
Constant-current charging represents
the ideal case. For practical purposes, it can be approximated with a sinusoidal source. In this case,
although the energy dissipation increases by a constant shape factor [3], the inverse relationship between
energy dissipation and charging time still holds.
The implementation of viable CMOS energy-recovery systems based on adiabatic charging has not
been a trivial task. First, adiabatic charging is associated with some circuit overhead, which potentially
cancels out the energy savings from adiabatic charging. Second, a key factor to implement an energyrecovery
system is the efficiency of the time-varying voltage source. Proposals for exploiting adiabatic
charging range from extreme reversible logic systems that theoretically can achieve asymptotically zero
energy dissipation [3,9] to more practical partial adiabatic approaches [10–16]. The former requires the
most overhead, both at the logic level and at the supply source level. The latter results in energy losses
2
asymptotic to CVth or CVVth
depending on the specific approach, where Vth
is the FET threshold voltage.
Their overhead is mostly at the logic level. Some of them can operate from a single time-varying supply
source [15,16].
In this chapter, we focus on clock-powered logic, which is a systematic approach for designing overall
energy-efficient CMOS VLSI systems that use adiabatic charging and energy recovery. The motivation
behind clock-powered logic is that the distribution of circuit nodes, excluding Vdd
and GND, for many
VLSI chips can be relatively identified as either large capacitance or small capacitance. Clock-powered
logic is a node-selective adiabatic approach, in which energy recovery through adiabatic charging is
applied to only those nodes that are deemed to be large capacitance. The circuitry overhead for energy
recovery and the adiabatic-charging process is amortized by the large capacitive load since energy savings
is proportional to the load. Nodes that are deemed small capacitance can be powered as they usually are
in CMOS circuits, e.g., precharging, pass-transistors networks, and static pull-up and pull-down networks
that draw power from a dc supply.
This article is organized as follows: First, section 21.2 reviews clock-powered logic followed by a
presentation of ac supply sources that can be used for adiabatic charging in section 21.3. In section 21.4,
an energy-recovery (E-R) latch is presented. The E-R latch is a key circuit used to pass energy from the
ac supply source to circuit data nodes and vice versa. Section 21.5 describes in detail how adiabaticallycharged
nodes interface with logic blocks powered from a dc supply voltage. In section 21.6, the drive
part of the E-R latch is compared to conventional drivers for energy versus delay performance through
HSPICE simulations. In section 21.7, two generations of clock-powered microprocessors are presented
and compared against an equivalent fully dissipative design. Finally, section 21.8 presents the conclusions.
T