U. Glaeser

(iv) Finally, while the processor completes an instruction, the temporary result held in the associated
rename register is written into the architectural register, which is specified in the destination field of the
instruction. The only tasks remaining are to delete the corresponding entry in the mapping table and to
reclaim the rename register associated with the completed instruction. Reclaiming of the rename register
is, however, a far more complex task than with issue bound operand fetching. Notice that if operands
are fetched issue bound, (a) issued instructions immediately access their operands and (b) missing
operands are, after their generation, immediately forwarded from the EU to the instructions waiting for
these operands in the RS. In this case, after completion of an instruction, the allocated rename register
can immediately be reclaimed. However, if operands are fetched during dispatching, the RS is not automatically
updated with the produced results. As a consequence, after an instruction completes, the RS may
still contain instructions, which will require the contents of the rename register, which is allocated to the
just completed instruction. Thus, while instructions complete, their allocated rename registers cannot be
reclaimed immediately as in the case of the issue bound operand fetching. To resolve this problem one
possible solution is to maintain a counter for each rename register, which keeps track of the number of
references made to this register. The counter will be incremented each time if one of the source operands
of an issued instruction addresses this particular rename register, and will be decremented during
dispatching of the instructions each time when a source operand is fetched from this register. After all
outstanding fetch requests for a particular rename register are satisfied, as indicated by the counter score
of zero, and the associated instruction has been completed, the related register becomes eligible for
reclaiming. At the first sight it may seem that this intricate reclaim process can be avoided if during
completion the RS would have been searched for all renamed source operand identifiers ( Rs1′ , Rs2′ ),
which refer to the rename buffer, allocated to the completing instruction (Rd′), and matching renamed
source register identifiers would have been remapped to the associated architectural register (Rd). Unfortunately,
this idea is not applicable, since there is no guarantee that the addressed architectural register
would not be rewritten until instructions needing its content are dispatched.
During the rename process rename registers will take the same states and the same state transitions
will also occur as described earlier in connection with Fig. 6.3. The only difference is that now rename
registers are reclaimed according to modified conditions, as discussed previously.
We emphasize that other basic alternatives of register renaming differ mainly in two aspects: (1) the
processor can hold renamed values in other structures than rename register files and (2) the processor
can use a different scheme for mapping the architectural registers to rename registers as assumed above.
In addition, the processor should be able to rename not just one instruction per cycle but all issued
instructions. Nevertheless, despite these differences, the previous descriptions in the two characteristic
scenarios give a good background about how the rename process is carried out in any of the possible
implementation schemes.
The Design Space of Register Renaming Techniques
Overview
The design space of register renaming has four main dimensions: the scope of register renaming, the layout
of the rename registers, the implementation technique of register mapping, and the rename rate, as
indicated in Fig. 6.5. These aspects are discussed in the subsequent sections. For the presentation of the
design space we make use of DS trees. 3,36
FIGURE 6.5 Design space of register renaming.
© 2002 by CRC Press LLC
Scope of
register renaming
Layout of the
rename buffers
Register renaming
Layout of the
register mapping
Rename rate