U. Glaeser

overflows of intermediate sums. That is, as the final result is correct even though intermediate sums may
be flawed.
For cases where higher dynamic ranges are needed, floating point solutions are employed. The floating
point representation of a real number X is given by X~(−1) S Mr E , where M is the mantissa, r the radix,
E is the signed exponent, and S is the sign bit. The mantissa is usually normalized to a value 1/r ≤ M < 1,
and the format is defined by published standards (e.g., IEEE). A variation on the floating-point theme
is called block floating point, a format used by a number of DSP chips, especially FFTs. A block floating
point representation of an array of numbers {x[k]} is defined in terms of a maximum exponent E, where
|x[k]| max = r E . A block floating point representation of the number x[k] is given by x[k] = ±M[k]r E , where
E is the fixed maximum exponent and M[k] is a fractional mantissa (M[k] ≤ 1). Since the scale factor r E
is known a priori, it need not be explicitly carried in number system representation.
The primary DSP arithmetic operation is the signed multiply accumulation (MAC). Fixed-point
multipliers cover a wide range of speed, precision, and complexity tradeoffs. Compact low-complexity
MACs can be designed using ripple adders. When adder area and power dissipation are not an issue,
carry-lookahead adders can be used to accelerate wide wordlength adders and, therefore improve MAC
speed. Carry-save adders (modified full adders) can also be an important element in implementing fast
multipliers. Another fast multiplier architecture is based on Booth’s algorithm and interprets strings of
consecutive of “ones” as multiplicative NO-OP operations. Fast multipliers can also be constructed using
arrays of small wordlength multipliers. These architectures are referred to as cellular array multipliers,
or simply array multipliers.
General-purpose programmable DSP µps make use of multipliers that map X∗Y → P, where X and Y
are variables. Most DSP applications, however, are SAXPY (S = A∗X + Y) intensive, which refers to
multiplying a variable X by a constant A (e.g., filter coefficients), followed by an accumulation. Implementing
SAXPY algorithms technically does not require general multiplication but rather an operation
called scaling. Several techniques have been developed to exploit scaling in the implementation of DSP
algorithms. They are particularly useful in implementing fixed-coefficient DSP algorithms with application
specific integrated circuits (ASIC), application specific standard parts (ASSP), and field-programmable
gate-arrays (FPGA) devices. One scaling technique is called the reduced adder graph (RAG) method. RAG
arithemtic is based on the theory of the ternary-valued ({0, ±1}) canonical sign-digit numbers (CSD).
For example, the 4-bit binary unsigned representation of the number 15 is 15 10 ↔ 1111 2, while the RAG
representation is given by 15 10 = 16 10 − 1 10 ↔ 1001 RAG, which can be implemented using one adder and
a shift register. The cost of an RAG multiplier is measured in terms of the number of adders needed to
complete a design. Another scaling method is called distribute arithmetic (DA) and is applicable only to
the implementation of constant DSP coefficient algorithms. As a point of reference, an Nth order FIR
digital filter, having known coefficients h r, r ∈ [0, N), requires N MAC operations be performed per cycle.
The data is assumed to be coded as an M-bit 2C word, where
where x[k:i] is the ith-bit of sample x[k]. The output y[k] is given by
where the mappings θ[ [k]:i] are implemented using 2 N x
-word memory lookups. The lookup table θ
maps an array of binary valued digits x[k:i] = { x[k:i],
x[k − 1:i],…,x[k − M−1:i]}, taken from the ith
© 2001 by CRC Press LLC
x[ k]
x[ k:0]
x[ k:1]2
1 – … x[ k:N– 1]2
N−1 –
= – + + +
N−1
∑
M−1
∑
y[ k]
hix[ k– r:0]
2 i –
= –
+
=
r=0
M−1
∑
θ[ x[ k]:0]
2 i
+
i=1
i=1
– θ x k
N−1
∑
r=0
[ [ ]:i]
( )
hr x[ k– r:i]