U. Glaeser

John George Maneatis
True Circuits Inc.
Fabian Klass
Sun Microsystems Inc.
Cyrus (Morteza) Afghahi
Broadcom Corporation
© 2002 by CRC Press LLC
10
Timing and Clocking
10.1 Design of High-Speed CMOS PLLs and DLLs
Introduction • PLL Architectures • Delay-Locked Loops •
Phase-Locked Loops • Advanced PLL Architectures •
DLL/PLL Performance Issues • DLL/PLL Circuits •
Differential Signal Conversion • Phase Detectors •
Self-Biased Techniques • Characterization Techniques •
Conclusions
10.2 Latches and Flip-Flops
Introduction • Timing Constraints • Design of Latches and
Flip-Flops • Scan Chain Design • Historical Perspective
and Summary • Appendix
10.3 High-Performance Embedded SRAM
Introduction • Embedded SRAM Design • Memory
Array • Testing and Reliability
10.1 Design of High-Speed CMOS PLLs and DLLs
John George Maneatis
Introduction
Phase-locked loops (PLLs), a set of circuits that include delay-locked loops, have found many applications
within the realm of microprocessors and digital chips in the past 15 years. These applications include clock
frequency synthesis, clock de-skewing, and high-bandwidth chip interfaces. A typical chip interface application
is shown in Fig. 10.1 in which two chips synchronously send data to one another. To achieve high
bandwidth, the data rate must be maximized with minimum data latency. Achieving this objective requires
careful control over system timing in order to guarantee that setup and hold times are always satisfied.
Let us consider the requirements for receiving data by Chip 2. Chip 1 transmits this data synchronously
along with a clock signal. Chip 2 would need to buffer this clock signal to drive all of the input latches
and use it to sample the data. Buffering the clock signal will introduce a delay that will vary with process and
environmental factors. The setup and hold time window for the input latches will then be shifted from
the input clock edge by this varying delay amount. Such a delay can make it very difficult to insure that
setup and hold times are always satisfied as the data rate is increased and this delay becomes a larger
fraction of the clock cycle.
To alleviate the situation, it is desirable to eliminate this clock distribution delay and center the setup
and hold time window on the input clock edge, which would remove any uncertainty in the window
position relative to the clock signal. Such an approach also has the added benefit of avoiding the necessity
for delay padding on the data wires to compensate for the clock distribution delay, which would increase
the latency. It is also desirable to be able to multiply the frequency of the clock signal for use in the chip
core so that the core logic can run with a higher clock frequency than available from the interface. These
objectives can all be accomplished with a PLL [1,2].