U. Glaeser

FIGURE 16.15 Dual threshold voltage domino logic gate.
chosen to have low V t, while noncritical gates would have high V t’s, with correspondingly lower leakage
currents [19]. This technique in general is only effective up to a certain point (diminishes with more critical
paths in the circuit), and determining which paths can be made high V t is a complex CAD problem [20].
An alternative application of dual V t technology that can be very useful in microprocessor design is
dual V t domino logic [21]. In this style, individual gates utilize both high V t and low V t transistors, and
the overall circuit will exhibit extremely low leakage in the standby mode, yet suffer no reduction in
performance. This is achieved by exploiting the fixed transition directions in domino logic, and assigning
a priori low-threshold voltages to only those devices in the critical charging/discharging paths. In effect,
devices that can switch during the evaluate mode should be low V t devices, while those devices that
switch during precharge modes should be high V t devices. Figure 16.15 shows a typical dual V t domino
stage used in a clock-delayed domino methodology, consisting of a pull-down network, inverter (I 1),
leaker device (P 1), and clock drivers (I 2, I 3), with the low V t devices shaded.
During normal circuit operation, critical gate transitions occur only through low V t devices, so highperformance
operation is maintained. On the other hand, precharge transitions occur only through high
V t devices, but since precharge times in domino circuits are not in the critical path, slower transition
times are acceptable. By having high V t precharge transistors, it is possible to place the dual V t domino
gate into a very low leakage standby state merely by placing the clock in the evaluate mode and asserting
the inputs. In a cascaded design with several levels of domino logic, the standby condition remains the
same, requiring only an assertion of the first-level inputs. The correct polarity signal will then propagate
throughout the logic to strongly turn off all high V t devices and ensure low subthreshold leakage currents.
In summary, dual V t domino logic allows one to trade-off slower precharge time for improved standby
leakage currents. As a result, using dual V t domino logic can achieve the performance of an all low V t
design, while maintaining the low standby leakage current of an all high V t design.
Adaptive Body Biasing (ABB)
Another technique to control subthreshold leakage is to modulate transistor V t’s directly through body
biasing. With application of maximum reverse body bias to transistors, threshold voltage increases,
resulting in lower subthreshold leakage currents during standby mode, but because the threshold voltage
can be set dynamically, this technique can also be used to adaptively bias a circuit block during the active
mode. Adaptive body biasing can be used to help compensate for large inter-die and within-die parameter
variations by tuning the threshold voltage so that a common target frequency is reached. By applying
reverse body bias to unnecessarily fast circuits, subthreshold leakage in the active mode can then be
reduced as well. In order to use this technique, the initial process V t should be targeted to a lower value
than desired, and then reverse body bias can be applied to achieve a higher threshold voltage mean with
lower variation.
Adaptive body biasing can easily be applied to a die as a whole (single PMOS body and NMOS body
bias values for the whole chip), which will tighten the distribution of chip delays and leakage currents
for a collection of dies, but because die sizes and parameter variations are becoming larger with future
scaling, within-die variation becomes a problem as well. ABB can be applied aggressively at the block
level, where individual functional blocks within a chip, such as a multiplier or ALU, can be independently
modulated to meet a common performance target. The following subsection, however, focuses on the
© 2002 by CRC Press LLC
Clk
2
n
D n
I 2
P1
I 3
I 1
Clk n+1
D n+1