U. Glaeser

Another way to reduce capacitance is to use the minimum possible width for metal interconnects that
carry AC signals such as clock and data buses. A study in electromigration research indicates that AC
interconnects can operate at much higher current density than design rules based on DC tests would
allow. It has been shown that electromigration lifetime is orders-of-magnitude longer under AC stress
than under DC stress. Similar behavior has also been reported for vias and other metal systems.
Yet another possible way to reduce metal capacitance would be to use insulators with lower permittivity
for inter-metal dieletrics. Relative to SiO 2 which has ε of ~4.2, SiOF has an ε of ~3.3 and organic polymers
may achieve an ε of ~2.5.
There appears to be no revolutionary low power device/technology, such as quantum devices, that is
manufacturable or compatible with mainstream circuit architectures today. The intrinsic speed-power
benefit of galium arsenide technology (GaAs) is probably not sufficient to overcome the difference in
cost and technology momentum with respect to silicon except for very high-speed circuits. Devices based
on quantum tunneling or single electron effect have excellent intrinsic switching speed and energy, but
they are not capable of driving the capacitance of long interconnects. In additon to the difficulty in
manufacturing, there are no suitable circuit architectures that are compatible with the characteristic of
these devices today. Fortunately, evolutionary innovations and optimization for low power plus continued
device scaling in silicon CMOS technology have been sufficient to support the need for low power ULSI
up to today, and hopefully for a long time into the future.
Power Reduction through Circuit Design
In general, power spent in the clock network is the largest contributor to the total power on highperformance
ICs such as a modern CPU, as indicated by the Fig. 14.2. The most effective impact for
reducing the total power is accomplished by reduction of switching capacitance on the clock network.
This is achieved through clock and data enabling (or gating). Clock gating is achieved by qualifying
different clock partitions by enable signals. Figure 14.10 illustrates the mechanics of clock gating and clock
networks. This in effect allows only the partitions that are active to toggle in each given cycle (Fig. 14.11).
FIGURE 14.10 Clock gating and clock networks.
FIGURE 14.11 Clock enabling.
© 2002 by CRC Press LLC
Global
Clk
A
D
Enable
Logic
Enable_A
PLL
(Clk generator)
Enable_B
Clk
Data
gated_clk
Enable_C
L
B
C
Comb.
Logic