U. Glaeser

provide a handful of gates and flip-flops to ones that provide well over a million gates. 1 In addition,
modern devices provide:
• Considerable on-chip memory: this partially overcomes an inability of early devices to effectively
solve problems that required more than a few memory bits
• Large numbers of I/O pins—permitting high data bandwidths between a custom processor and
its environment
• Multiple I/O protocols, such as LVDS, GTL, and LVPECL—enabling high speed serial channels
between the device and other components of a system
Programmability may be provided by a number of technologies:
• Fuses or anti-fuses, in which links are programmed open or closed
• EEPROM, in which a configuration bit is stored in nonvolatile read-only memory, and
• Static RAM cells, which store configuration bits, but, which need to be reloaded every time the
device is powered up
Thus, a designer has a broad palette of devices on which to base a system design. All the usual trade-offs
apply: in particular, the ability to change the circuit by reprogramming it invariably introduces a speed
penalty. A configurable circuit is more complex and has longer propagation delays than a fixed one: this
translates to a slower maximum clock frequency. This trade-off is discussed further when we consider
whether an application is a good candidate for a reconfigurable processor compared to a general-purpose
commodity processor.
A number of terms have been used to describe programmable devices. Simple early devices (ones with
a simple programmable and-or array, coupled with ~10 flip-flops and ~20 I/O pins) were commonly called
“programmable array logic” chips or PALs, but a host of other similar terms have been used for marketing
purposes. The most important group of devices for building processors are now almost universally termed
“field programmable gate arrays” (FPGAs) 2 and this chapter section will focus on them as the key building
blocks of a reconfigurable system. As with general-purpose processors, designing a “universal” FPGA is
essentially an impossible task and a number of different architectural styles have been proposed and
manufactured. The following subsections will describe the key elements of some representative devices.
FPGA Architectures
An FPGA’s capability can usually be described in terms of three elements:
1
•
•
Logic blocks:
These are small blocks of logic, commonly consisting of a small number of simple
and-or arrays, some multiplexers for steering signals, one or two flip-flops. Other features such as
memory bits, lookup tables, special logic for handling the carry chains in adders, etc., may be
present also. Marketing pressures have produced a bewildering array of names for these blocks:
fortunately, most of them are readily understood. Examples are logic array blocks (Altera APEX
20k family), logic elements (Altera FLEX 10KE), macrocells (Altera MAX7000/MAX3000), configurable
logic blocks (Xilinx), and programmable function units (Lucent ORCA).
Routing resources:
A typical FPGA will provide lines of various lengths to interconnect the logic
blocks. Short lines provide low propagation delay paths between neighbouring blocks; longer lines
connect more distant blocks with low delay. A small number of buffered low delay lines, which
can interconnect large groups of logic blocks are usually provided for clocks.
2001 value: apply Moore’s Law for 2002 and forward.
2
Market habits die hard, though: Altera persists in referring to its devices as programmable logic devices (PLDs).
© 2002 by CRC Press LLC