U. Glaeser

measured in megabits, not megabytes. Although external memory can always be added and wide
buses employed to provide high bandwidth, this uses valuable I/O pins, the path to external memory
is likely to become a bottleneck and limit performance.
(c) “ Decision-free”
processing patterns: Multiplexors in the data paths will readily handle simple decisions,
which switch the dataflow between down-line functional blocks, but complex decision trees
will generally not map efficiently to hardware. When large numbers of branches exist, inevitably
many paths are little used and thus expensive to implement in fixed hardware relative to their
benefit. In particular, error handling logic will generally be complex relative to its frequency of
use. Complex decision logic is efficiently handled in high-performance modern processors, which
move common logic to cache at the expense of little used code. When branches have similar
probabilities, speculative execution ensures good average rates of instruction completion. However,
this criterion for successful hardware implementation should be applied with caution: if high
throughput for all possible processing paths is required, then the resources devoted to implementing
all paths (including little used ones) may be justified. In the near future, dynamically reconfigurable
logic may also provide effective solutions when there are complex decision trees.
(d) Ability to use local (i.e., between neighbouring devices) data paths in problems that are large
enough to require multiple devices. Most systems provide high-bandwidth paths between nearest
neighbors with lower-bandwidth multiple device buses and global interconnects. The 3-D Achilles
design provides more device–device data path flexibility but at a cost—wiring patterns must be
set up manually for each application [14].
(e) Integer arithmetic: Although it is possible to implement arbitrary precision floating-point processors
in FPGAs, the number of logic blocks required and hence the delays introduced by data paths
between logic blocks make them expensive in area and low in performance compared to those
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found in superscalar processors. On the other hand, the ability to easily implement arbitrary
precision integer arithmetic allows a reconfigurable system designer to pack more functional units
of higher performance into a given area by choosing the minimum required word length.
Image Processing
Real-time image processing presents a classic application for custom processors. A stream of pixels
emanating from a camera can be passed through a wide deep pipeline—performing as many unrelated
and complex operations on each pixel as needed. Unrelated operations (e.g., threshholding and masking)
are performed in parallel and complex operations (e.g., masking) are performed in deep pipelines. For
basic operations, little storage is required and the relatively inefficient memory on an FPGA suffices. A
masking operation, such as applying a 3 × 3 mask to a group of neighboring pixels, requires the storage
of two scanlines in a shift register and thus is feasible in large FPGAs. The reverse process, visualisation, or
the processing of machine generated images for display is already the domain of special purpose proces-
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sors, but market volumes have justified use of ASICs.
Stereo Vision
The matching problem dominates research into fully automated stereo vision systems; it requires the
comparison of pixels (or regions of pixels) to determine matches between corresponding segments of two
images. The distance between matching regions on the left and right images (the disparity) is combined
with camera system geometry to determine the distance to objects in the field of view. Without the apparent
ability of a human brain to “jump” to the obvious match, a machine must try all possible disparities in
order to find candidate matches between pixels or to correlate regions. Objects close to the camera system
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Superscalar processor manufacturers are also prepared to invest large amounts in order to win benchmark competitions,
which allows man-years of effort to be used to optimize individual circuits and layouts.
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However, prototyping designs which are destined for ASICs are a major application for reconfigurable processors.
They can be used to ensure that a design is correct and that the silicon will function correctly first time. Some foundries
will take FPGA-based designs and convert them directly to ASICs.
© 2002 by CRC Press LLC