U. Glaeser

pass-transistor logic, constrained that all source signals must terminate to V dd or GND. This unnecessary
constraint is removed in PTL, but at the same time complexity of designing large PTL circuits is increased.
The most area-efficient method to synthesis of large PTL networks is decomposition into fundamental
units with small number of inputs, typically two or three. To illustrate this, the synthesis of random logic
function using three different mapping techniques is analyzed.
Consider the function
© 2002 by CRC Press LLC
TABLE 2.2 Comparison of Different Realizations of 3-Input Function F = B′C + ABC′ [22]
Realization No. of Input Signals Signal Termination Transistor Count Output Load
CMOS 9 10G 10 4S
DVL (e) 9 8G + 6S 8 6S
DVL (f) 9 7G + 3S 7 4S
BC
A 00 01
0
A 1
0 1
0 1
B
C
B C
C
11 10
B
C
0 0
0 1
C2 B
C1
A
A B C
(d)
F
BC
A 00 01
0
A 1
B
0 1
0 1
C
11 10
FIGURE 2.74 Karnaugh map coverage of 3-input function in (a) complementary CMOS, (b) DVL, (c) DVL and
corresponding circuit realizations in (d) complementary CMOS, (e) DVL, and (f) DVL [22].
(2.2)
and its three different realizations shown in Fig. 2.74. All three circuits implement the same function,
but have different total active switching capacitance and different energy consumption. This example is
extension of the analysis provided in [11] towards generalization of random logic function synthesis.
Realization in complementary CMOS, Fig. 2.74(d), has smaller load on input signals and internal output
load than the DVL realization in Fig. 2.74(e). Two realizations of DVL show different mapping strategies:
the first strategy is to cover the map with largest possible cubes, Fig. 2.74(b), while the second strategy,
Fig. 2.74(c), is based on map decomposition and reduction to implementation of basic 2-input functions.
The DVL realization in Fig. 2.74(f) has smallest total load on input signals and similar internal output
load as complementary CMOS realization, as shown in Table 2.2.
This example illustrates the importance of strategy used to cover Karnaugh map and leads to a
conclusion that functional decomposition is the most efficient method in PTL circuit optimization.
Straightforward coverage of Karnaugh map with largest cubes, as shown in Fig. 2.74(b) results in a circuit
with lower performance, Fig. 2.74(e), while more careful coverage with decomposition of inputs, Fig. 2.74(c),
results in a circuit with both smaller transistor stack and smaller transistor count, Fig. 2.74(f).
0 0
0 1
BC
A 00 01
0 1
0 1
C1 C B
2
C
C1 3
C2 C
C
B
B
C
B C B
C
B
C
A
A
F
C
0
A 1
(a) (b) (c)
Vdd C 2
C 1
C 1
C 1
C 2
C 2
C 3
C 3
F = BC+ ABC
C 3
(e) (f)
F =
B⋅C+ A⋅ B⋅ C
C
11 10
C
0 0
0 1
B
B B
B
C
A
C 3
C 2
F
B
C
C 3