U. Glaeser

FIGURE 10.53 Transparent-high latches built from pass gates and transmission gates.
FIGURE 10.54 Feedback structures for latches.
noise: a noise spike can turn momentarily the gate on, or can inject charge in the substrate by turning
the parasitic diode on, leading to a charge loss. To make this design more robust, each of the variants in
Fig. 10.53 (b-f) attempts to overcome at least one of the limitations just described. Figure 10.53(b) uses
a transmission gate to avoid the threshold voltage drop, at the expense of generating a complementary
clock signal [12,13]. Figure 10.53(c) buffers the output to protect the storage node and to improve the
output drive. Figure 10.53(d) uses a back-to-back inverter to prevent the storage node from floating.
Avoiding node Q in the feedback loop, as shown, improves robustness by completely isolating the output
from the storage node, at the expense of a small additional inverter. Figure 10.53(e) buffers the input in
order to: (1) improve noise immunity, (2) ensure the writability of the latch, and (3) bound the D-to-Q
delay (which depends on the size of input driver). Conditions 2 and 3 are important if the latch is to be
instantiated in unpredictable contexts, e.g., as a library element. Condition 2 becomes irrelevant if a
clocked feedback is used instead. It should be noted that the additional input inverter results in increased
D-to-Q delay; however, it need not be an inverter, and logic functionality may be provided instead with
the latch. Figure 10.53(f) shows such an instance, where a NAND2 gate is merged with the latch. A
transmission gate latch, where both input and output buffers can be logic gates, is reported in [11].
Feedback Circuits
A feedback circuit in latches can be built in more than one way. The most straightforward way is the back
inverter, adopted in Fig. 10.53(d–f), and shown in detail in Fig. 10.54(a). Clock CKB is the complementary
of clock CK. The back inverter is sized to be weak, in general by using minimum size transistors, or
increasing channel length. It must allow the input driver to overwrite the storage node, yet it must provide
enough charge to prevent it from floating when the latch is opaque. Although simple and compact layoutwise,
this type of feedback requires designers to check carefully writability, especially in skewed process
corners (e.g., fast PMOS, slow NMOS) and under different temperature and voltage conditions. A more
robust approach is shown in Fig. 10.54(b). The feedback loop is open when the storage node is driven,
eliminating all contention. It requires additional devices, although not necessarily more area since the
input driver may be downsized. A third approach is shown in Fig. 10.54(c) [12]. It uses a back inverter
but connecting the rails to the clock signals CK and CKB. When the latch is opaque, CK is low and CKB
© 2002 by CRC Press LLC
D
D
Q
D
CK
CK
CK
(a) (b) (c)
QB D
Q
CK
CK
D1 D2 CK
(d) (e) (f)
weak inverter
CKB
CKB
CK
CK
(a)
CK CKB
(b)
Q
D
CKB
CKB
CK
CK
(c)
QB
Q