U. Glaeser

when used as a flip-flop, the NAND3 is skewed favoring the high-to-low transition, while the middle
stack is complementary. This is because if the middle stack were skewed, favoring the low-to-high transition,
the opposite transition would become critical. When the circuit is used as a transparent latch, all
stages are static. (i.e., both transitions are balanced). The worst-case transition in this case is opposite
to that shown in Fig. 10.74: input D is switching and the total delay is equal to 1.2 + 1.5 + 1.2 = 3.9. In
the case of SDFF (Fig. 10.74(j)), since the middle stack is shorter, both the first stage (precharged) and
the middle stack are skewed.
A similar procedure to the one described above is followed to compute the minimum CK-to-Q delay.
An additional assumption is that the output buffer has FO1 as opposed to FO4 as in max-timing, which
results in shorter delay. The normalized FO1 pull-up delay of a buffer is 0.6 (PMOS), and the pull-down
is 0.5 (NMOS).
To compute hold time the following assumptions are made. The inverters used in inverting or delaying
clock signals, with the exception of external pulse generators (see Fig. 10.65), have FO1, so their delays
are those of the previous paragraph. External pulse generators use three FO4 inverters instead (i.e., slower),
because in practical designs it is very hard to create a full-rail pulse waveforms with less delay. For
transparent-high latches, the hold time is defined as the time from CK switching high-to-low until all
shutoff devices are completely turned off. To insure the shutoff device is completely off, 50% delay is
added to the last clock driver. For instance, the hold time of the transparent-low transmission gate latch
is 0.5 (FO1 inverter delay) × 1.5 = 0.75. For a positive edge-triggered flip-flop, the hold time is defined
as the time from CK switching low-to-high until all shutoff devices are completely turned off. If there is
one or more stages before the shutoff device, the corresponding delay is subtracted from the hold time.
This is the case of the buffered master-slave flip-flop (Fig. 10.74(e)), which results in a negative hold
time. An exception to this definition is the case of HLFF or SDFF. Here, the timing of the shutoff device
must allow that the stack gets fully discharged. Therefore, the hold time is limited by the stack delay,
which is again defined as 1.5 times the stage delay. For instance, for HLFF, the middle stage pull-down
delay is 1.3, so the hold time is 1.5 × 1.3 = 1.95. SDFF, instead, has its hold time determined by the timing
of the shutoff device because the precharged stage is fast.
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