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U. Glaeser

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45.4 Summary<br />

Automatic test pattern generation yielding high fault coverage for CMOS circuits has received wide<br />

attention in industry and academia for a long time. Mixed-level test pattern generation offers advantages,<br />

since test generation from gate-level netlists has shortcomings regarding fault coverage in complex CMOS<br />

gates. A switch-level approach relying on the transistor structure only is too slow and impractical for<br />

larger circuits. The first part of this chapter describes automatic test pattern generation with a mixed<br />

switch-level and gate-level approach. It combines acceptable performance for large networks with a high<br />

fault coverage also for nontrivial transistor networks. Patterns generated this way are inherently capable<br />

to detect stuck-open faults and transition faults as well as various other fault models on different<br />

abstraction levels. In combination with local overcurrent detectors, also stuck-on and local bridging faults<br />

can be identified. To increase the efficiency of mixed-level test generation, a reconvergency analysis is<br />

performed and constraints are stored.<br />

An original approach to test generation for synchronous sequential circuits was presented. Two levels<br />

of hierarchy, the switch-level and the gate-level are supported. Inter-level backtracks between these two<br />

hierarchies are implemented. The number of inter-level backtracks is minimized using simple heuristics<br />

for constraint identification, which is a promising method for hierarchical test generation also on higher<br />

levels (RT or behavior level). A new efficient algorithm called FOGBUSTER for the forward propagation<br />

backward initialization technique handles synchronous sequential circuits. A 4-valued logic and a twostaged<br />

backtracking mechanism are used to handle the over-specification problem and to achieve completeness.<br />

Experimental results for the ISCAS ’85 and ISCAS ’89 benchmark circuits are encouraging. In<br />

comparison to the BACK-algorithm and to the HITEC approach, FOGBUSTER on the average has a<br />

significantly better performance.<br />

References<br />

1. H. Fujiwara, T. Shimono: On the acceleration of test generation algorithms, IEEE Trans. on Computers<br />

(C-32), 1983, pp. 1137–1144.<br />

2. M. H. Schulz, E. Trischler, T. M. Sarfert: SOCRATES: A highly efficient ATPG system, IEEE Trans.<br />

CAD, Vol. 7, Jan. 1988, pp. 126–137.<br />

3. J. P. Roth: Diagnosis of Automata Failures: A calculus and a method, IBM Journal, 1966, pp. 278– 291.<br />

4. M. H. Schulz, E. Auth: Essential: An efficient self-learning test pattern generation algorithm for<br />

sequential circuits, Proc. IEEE Int. Test Conf., 1989, pp. 28–37.<br />

5. N. Gouders, R. Kaibel: Advanced techniques for sequential test generation, Proc. 2nd European Test<br />

Conf., Munich, 1991.<br />

6. R. L. Wadsack: Fault modeling and logic simulation in CMOS and MOS integrated circuits, Bell<br />

Systems Technical Journal, May–June 1978, pp. 1449–1474.<br />

7. F. Ferguson, J. Shen: Extraction and simulation of realistic CMOS faults under inductive fault<br />

analysis, Proc. IEEE Int. Test Conf., 1988, pp. 475–484.<br />

8. H. T. Vierhaus: Testability of CMOS faults under realistic conditions, Microprocessing and Microprogramming,<br />

Vol. 27, pp. 681–686, 1989.<br />

9. U. <strong>Glaeser</strong>, U. Hübner, H. T. Vierhaus: mixed level hierarchical test generation for transition faults<br />

and overcurrent related defects, Proc. ITC ’92, pp. 21–29.<br />

10. U. <strong>Glaeser</strong>, H. T. Vierhaus: MILEF: an efficient approach to mixed level automatic test pattern<br />

generation, Proc. EURODAC ’92, pp. 318–321.<br />

11. K. W. Chiag, Z. G. Vranesic: on fault detection in CMOS logic networks, Proc. IEEE Int. Test Conf.,<br />

1983, pp. 50–56.<br />

12. C. Glover: Mixed mode ATPG under input constraints, Proc. IEEE Int. Test Conf., 1990.<br />

13. M. L. Flottes, C. Landrault et al.: Mixed level automatic test pattern generation for CMOS, Proc.<br />

2nd European Test Conf., Munich, 1991, pp. 273–282.<br />

© 2002 by CRC Press LLC

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