U. Glaeser

I/O Pads, is 60 mW for the multiplexer and 80 mW for the demultiplexer, both from −2 V power supply.
The multiplexer occupies 0.132 mm 2 , and the demultiplexer occupies 0.163 mm 2 , both without I/O Pads.
Measured eye diagrams at the outputs are also presented in Figs. 3.19 and 3.20. Figure 3.21 shows the
error-free maximum operating speed of 1.65 Gb/s for the multiplexer and 1.80 Gb/s for the demultiplexer.
The LV-ECL circuit tolerates ±5% variations in supply voltage with no significant degradation in speed.
In these tests, a pseudo-random bit sequence of length 2 23 − 1 is applied at the input. V OH shows 1.4 mV/°C
temperature dependence, the same as that in the conventional ECL. V OL exhibits −0.7 mV/°C over a range
of 0–75°C, and 3 mV/°C for the range of 75–125°C. As a consequence, the output voltage swing is 0.17 V
© 2002 by CRC Press LLC
TABLE 3.1 4:1 MUX Gate Performance Comparison
Min. VEE
(V)
Power
(mW)
Delay
(ps)
PD
(pJ)
Element
Tran.
Count
Res.
Conventional ECL
3-level series gating −4.0 5.6 440 2.46 29 9
2-level series gating −3.1 9.3 440 4.14 45 21
LV-ECL −2.0 3.2 460 1.47 26 21
FIGURE 3.17 4:1 MUX gate in LV-ECL.
FIGURE 3.18 Toggle flip-flop in LV-ECL.